Architecture and Applications of DSP Edutech Systems About

Architecture and Applications of DSP Edutech Systems

About Edutech Systems n n n Interactive Learning Resource Development Company Offers Learning Resources for Embedded and DSP learning Firmware development Hardware consultancy services Training

Learning Resources n n n n Tutors, CBT, WBT etc Simulators Compilers Programmers, Debuggers, Emulators CPU boards Interfacing Modules Laboratory Workbooks

What is Embedded System? n “An embedded system is an application that contains at least one programmable computer typically in the form of a microcontroller, a microprocessor or digital signal processor chip

Examples of Embedded Systems Examples of embedded systems are n Controller in washing machine, n Controller in compact disk player, n The navigation system in an aircraft, n The controller of a robot arm.

How ES are characterized? ESs are a special class of electronic systems that can be briefly characterized by following terms: n Single-functioned n n Tightly-constrained n n Executes a single program, repeatedly Low cost, low power, small, fast, etc. Reactive and real-time n n Continually reacts to changes in the system’s environment Must compute certain results in real-time without delay

A “short list” of Embedded Systems n n n Automotive electronics Aircraft electronics Railways Telecommunication Medical systems Military applications Authentication circuits Consumer electronics Fabrication equipment Smart buildings Robotics

Embedded System Structure

Digital Signal Processing n n Digital Signal Processing (DSP) is concerned with the digital representation of signals Digital signal processing is the mathematical manipulation of an information signal to modify or improve it in some way. Digital signal processing and analog signal processing are subfields of signal processing. The goal of DSP is usually to measure, filter and/or compress continuous real-world analog signals.

Digital Signal Processor n DSP algorithms have long been run on standard computers, on specialized processors called digital signal processor which is a specialized microprocessor with an architecture optimized for the operational needs of digital signal processing. Analog Signal ADC Digital Signal Processing DAC Analog Signal

Applications of Digital Signal Processing n n n n n Audio and speech signal processing Sonar and radar signal processing Sensor array processing Spectral estimation Statistical signal processing Digital image processing Signal processing for communications Control of systems Biomedical signal processing Speech codec in cell phone

Overview of Signal Processing n n The goal of DSP is usually to measure, filter and/or compress continuous real-world analog signals. Analog signals typically vary continuously with time; however, in order to process analog signals with a CPU, we must first acquire digital samples to be processed. When samples of a continuous input signal are captured as digital data, a waveform is considered a discrete time signal.

Overview of Signal Processing n n n The time between the samples is known as the sampling period. The sampling period is usually constant for a particular signal being sampled. The reciprocal of the sampling period is known as the sampling frequency fs. The sampling frequency must be at least twice the bandwidth of the signal being processed according to the Nyquist sampling theorem. Examples: Traditional telephony signals: 4 KHz, fs=8 KHz, samples every 125 ms Wideband telephony signals: 8 KHz, fs=16 KHz, samples every 62. 5 ms CD audio signals: 22 KHz, fs=44 KHz, samples every 27 ms

DSP Building Blocks n n Digital signal processing algorithms are typically built up from three basic functions: Add, Multiply, and Delay. The first function is an adder; it adds samples of two or more discrete time signals. Samples are added for all values of n, as shown in figure

DSP Building Blocks (Contd. ) n The second function is the multiplier; the multiply block scales all samples in the discrete time signal by the same scaling factor, as shown in figure.

DSP Building Blocks (Contd. ) n The third key building block for a DSP algorithm is a delay function. The delay function shifts the samples to the right.

DSP Building Blocks (Contd. ) n Feed forward System n Feedback System

Data Acquisition n n The A/D converts the sample analog signal and provides an integer value representing the signal sampled. There a wide range of A/D converters available with varying resolutions. The resolution is defined by the number of bits used to represent the full range of the sampled signal; common resolutions are 8, 10, 11, 12, 14, 16, and 24 bits. For audio sample acquisition component known as codec is attached via the HD audio interface. The Real. Tek Codec is such a device that can be used to convert between the analog audio domain and the digital domain of the processor.

DSP Algorithm Implementation DSP Algorithm Fixed Point n n Floating Point For example, a 16 -bit integer can represent a maximum range of 65, 536. Floating-point implementations, on the other hand, can represent a much larger dynamic range, as floating-point representations are designed to represent both very small and very large numbers. Under certain standardization a 32 -bit floating-point (single precision) positive number has a range of 2 -149 to 3. 403 X 1038.

Fixed Point Vs Floating Point Selection n n Different numeric formats Cost Vs ease of use Floating point computational accuracy (e. g. Radar for navigational aid) Data set decision Mathematical flexibility

COMPARISION BETWEEN DSPS & MICROCONTROLLER n n n Microcontrollers and Digital Signal Processors (DSPs) are the main engines of the deeply embedded development world. A MICROCONTROLLER is a highly integrated chip which includes, on one chip, all or most of the parts needed for a controller, is used to control some process or aspect of the environment. The microcontroller could be called a "one-chip solution". DSPs are a highspeed single chip microprocessor or microcomputer designed to perform computer intensive digital signal processing tasks. Microcontrollers are primarily used in control-oriented applications that are interrupt-driven, sensing and controlling external events. DSPs, meanwhile, are traditionally found in systems that require the precision processing of analog signals. Microcontrollers are inexpensive, small, and flexible. DSP is larger, more expensive, and more specialized.

Introduction to DSP C 6748 n n n 375 - and 456 -MHz C 674 x Fixed- and Floating-Point VLIW DSP C 674 x Instruction Set Features n Superset of the C 67 x+ and C 64 x+ ISAs n Up to 3648 MIPS and 2746 MFLOPS n Byte-Addressable (8 -, 16 -, 32 -, and 64 -Bit Data) n 8 -Bit Overflow Protection n Bit-Field Extract, Set, Clear n Normalization, Saturation, Bit-Counting n Compact 16 -Bit Instructions C 674 x Two-Level Cache Memory Architecture n 32 KB of L 1 P Program RAM/Cache n 32 KB of L 1 D Data RAM/Cache n 256 KB of L 2 Unified Mapped RAM/Cache n Flexible RAM/Cache Partition (L 1 and L 2)

Features n n Enhanced Direct Memory Access Controller 3 (EDMA 3): n 2 Channel Controllers n 3 Transfer Controllers n 64 Independent DMA Channels n 16 Quick DMA Channels n Programmable Transfer Burst Size TMS 320 C 674 x Floating-Point VLIW DSP Core n Load-Store Architecture with Nonaligned Support n 64 General-Purpose Registers (32 -Bit) n Six ALU (32 - and 40 -Bit) Functional Units n Supports 32 -Bit Integer, SP (IEEE Single Precision/32 -Bit) and DP (IEEE Double Precision/64 -Bit) Floating Point n Supports up to Four SP Additions Per Clock, Four DP Additions Every Two Clocks n Supports up to Two Floating-Point (SP or DP) Reciprocal Approximation (RCPx. P) and Square-Root Reciprocal Approximation (RSQRx. P) Operations Per Cycle

Features Two Multiply Functional Units: n Mixed-Precision IEEE Floating-Point Multiply Supported up to: n 2 SP x SP → SP Per Clock n 2 SP x SP → DP Every Two Clocks n 2 SP x DP → DP Every Three Clocks n 2 DP x DP → DP Every Four Clocks n Fixed-Point Multiply Supports Two 32 x 32 -Bit Multiplies, Four 16 x 16 -Bit Multiplies, or Eight 8 x 8 -Bit Multiplies per Clock Cycle, and Complex Multiples n Instruction Packing Reduces Code Size n All Instructions Conditional n Hardware Support for Modulo Loop Operation n Protected Mode Operation n Exceptions Support for Error Detection and Program Redirection Software Support n TI DSPBIOS n Chip Support Library and DSP Library n n

Features n n n n 128 KB of RAM Shared Memory 1. 8 -V or 3. 3 -V LVCMOS I/Os (Except for USB and DDR 2 Interfaces) Two External Memory Interfaces: n EMIFA n NOR (8 - or 16 -Bit-Wide Data) n NAND (8 - or 16 -Bit-Wide Data) n 16 -Bit SDRAM with 128 -MB Address Space n DDR 2/Mobile DDR Memory Controller with one of the following: n 16 -Bit DDR 2 SDRAM with 256 -MB Address Space n 16 -Bit m. DDR SDRAM with 256 -MB Address Space Three Configurable 16550 -Type UART Modules: n With Modem Control Signals n 16 -Byte FIFO n 16 x or 13 x Oversampling Option LCD Controller Two Serial Peripheral Interfaces (SPIs) Each with Multiple Chip Selects Two Multimedia Card (MMC)/Secure Digital (SD) Card Interfaces with Secure Data I/O (SDIO) Interfaces

Features n n n Two Master and Slave Inter-Integrated Circuits (I 2 C Bus) One Host-Port Interface (HPI) with 16 -Bit-Wide Muxed Address and Data Bus For High Bandwidth Programmable Real-Time Unit Subsystem (PRUSS) n Two Independent Programmable Real-Time Unit (PRU) Cores n 32 -Bit Load-Store RISC Architecture n 4 KB of Instruction RAM Per Core n 512 Bytes of Data RAM Per Core n PRUSS can be Disabled via Software to Save Power n Register 30 of Each PRU is Exported From the Subsystem in Addition to the Normal R 31 Output of the PRU Cores. n Standard Power-Management Mechanism n Clock Gating n Entire Subsystem Under a Single PSC Clock Gating Domain n Dedicated Interrupt Controller n Dedicated Switched Central Resource

Features n n USB 1. 1 OHCI (Host) with Integrated PHY (USB 1) USB 2. 0 OTG Port with Integrated PHY (USB 0) n USB 2. 0 High- and Full-Speed Client n USB 2. 0 High-, Full-, and Low-Speed Host n End Point 0 (Control) n End Points 1, 2, 3, 4 (Control, Bulk, Interrupt, or ISOC) RX and TX One Multichannel Audio Serial Port (Mc. ASP): n Two Clock Zones and 16 Serial Data Pins n Supports TDM, I 2 S, and Similar Formats n DIT-Capable n FIFO Buffers for Transmit and Receive Two Multichannel Buffered Serial Ports (Mc. BSPs): n Supports TDM, I 2 S, and Similar Formats n AC 97 Audio Codec Interface n Telecom Interfaces (ST-Bus, H 100) n 128 -Channel TDM n FIFO Buffers for Transmit and Receive

Features n n 10/100 Mbps Ethernet MAC (EMAC): n IEEE 802. 3 Compliant n MII Media-Independent Interface n RMII Reduced Media-Independent Interface n Management Data I/O (MDIO) Module Video Port Interface (VPIF): n Two 8 -Bit SD (BT. 656), Single 16 -Bit or Single Raw (8 -, 10 -, and 12 -Bit) Video Capture Channels n Two 8 -Bit SD (BT. 656), Single 16 -Bit Video Display Channels Universal Parallel Port (u. PP): n High-Speed Parallel Interface to FPGAs and Data Converters n Data Width on Both Channels is 8 - to 16 -Bit Inclusive n Single-Data Rate or Dual-Data Rate Transfers n Supports Multiple Interfaces with START, ENABLE, and WAIT Controls Serial ATA (SATA) Controller: n Supports SATA I (1. 5 Gbps) and SATA II (3. 0 Gbps) n Supports All SATA Power-Management Features

Features n n n Real-Time Clock (RTC) with 32 -k. Hz Oscillator and Separate Power Rail Three 64 -Bit General-Purpose Timers (Each Configurable as Two 32 -Bit Timers) One 64 -Bit General-Purpose or Watchdog Timer (Configurable as Two 32 -Bit General. Purpose Timers) Two Enhanced High-Resolution Pulse Width Modulators (e. HRPWMs): n Dedicated 16 -Bit Time-Base Counter with Period and Frequency Control n 6 Single-Edge Outputs, 6 Dual-Edge Symmetric Outputs, or 3 Dual-Edge Asymmetric Outputs n Dead-Band Generation n PWM Chopping by High-Frequency Carrier n Trip Zone Input Packages: n 361 -Ball Pb-Free Plastic Ball Grid Array (PBGA) [ZCE Suffix], 0. 65 -mm Ball Pitch n 361 -Ball Pb-Free PBGA [ZWT Suffix], 0. 80 -mm Ball Pitch Commercial, Extended, or Industrial Temperature

DSP C 6748 Block Diagram

Introduction to EPB_C 6748

EPB_C 6748 Features Mechanical Parameters n Size: 160 mm x 136 mm n Input Voltage - 5 V DC Processor n TMS 320 C 6748 – Fixed/ Floating Point Digital Signal Processor n DSP with up to 456 MHz performance. n On board 14 Pin (2 x 7 Pin) JTAG emulation connector n Boot mode selection switch Memory n On board 256 MB Flash memory n On board 128 MB DDR 2 RAM memory

EPB_C 6748 Features Data Transfer Interfaces n On board DB 9 connector for UART-1 interface n On board 3 pin header for UART-2 interface n On board USB TYPE B Connector for UART-2 interface for Debug Console n LED indication for USB connection for Debug Console n On board Reset Switch with LED indication n On board USB Type A Connector for USB host interface n On board micro USB Type A Connector for USB OTG interface n On board RJ 45 connector for 10/100 Ethernet interface n On board I 2 C based Temperature sensor n On board I 2 C based RTC interface with battery backup n On board SPI based micro SD card interface n On board SATA connector

EPB_C 6748 Features Input/Output Interfaces and other Facilities n On board Power-On LED indication n On board 4 User LED at GPIO Pin as GPIO Test point n On board 5 user push buttons for various applications Special functionality n Boot mode selection switch n On board Video in and Video out port available n On board VGA out connector n On board Graphics LCD interface connector n On board audio jack and speaker(Mic in) interface and audio coded for speaker out n On board CMOS sensor connector to interface CMOS camera n On board Temperature sensor with interrupt out facility n On board LED to indicate high voltage input n On board excessive voltage protection circuit with LED indication n Various test points for various signals

Hands-On Session with C 6748 n n n n Creating a New Project Introduction to command file Introduction to Gel File Basic DSP based Examples Filter Examples Image Processing Video Processing

Thank You. . ! n Thank you. . !

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