APPENDIX B SYSTEM DEVELOPMENT Appendix B System Development

APPENDIX B: SYSTEM DEVELOPMENT Appendix B: System Development Example MTT 48 V 2. 1 B - 1

68 HC 08 SYSTEM EXAMPLE Simple application set up • Power On / Reset • CPU Initialization • Memory initialization Appendix B: System Development Example MTT 48 V 2. 1 B - 3

APPLICATION DESCRIPTION Basic automotive instrument cluster panel • Displays PRNDL setting based on 3 discrete inputs – Port A PTA 2 PTA 0 • Calculates and displays vehicle speed by measuring a pulse frequency – 1 Pulse indicates 1 revolution of wheel axle – Input on timer channel 1 • Receives data relating to warning lamps from powertrain control module via SCI at 9600 baud – Eight warning lamp discrete outputs on Port B (Engine over temp, low oil pressure, low fuel, service engine, etc. ) Appendix B: System Development Example MTT 48 V 2. 1 B - 4

APPLICATION DESCRIPTION (CONT. ) • Receives battery voltage, coolant temperature, and outside air temperature values from 8 bit A/D converter via SPI – Port A Bit 7 as SS line for A/D • Key in ignition generates an external Interrupt on IRQ 2 • 4 MHz external crystal and desire 8 MHz bus frequency Appendix B: System Development Example MTT 48 V 2. 1 B - 5

INSTRUMENT PANEL CONTROLLER 8 Bit A/D 68 HC 708 XL 36 Axle Ref. Pulses Key in ignition Warning Light 1 Warning Light 2 Warning Light 3 Warning Light 4 Warning Light 5 Warning Light 6 Warning Light 7 Warning Light 8 PTA 7 TCH 1 IRQ 2 PTB 0 PTB 1 PTB 2 PTB 3 PTB 4 PTB 5 PTB 6 PTB 7 SPSCK MOSI MISO (SCI) TXD (SCI) RXD SS Battery Voltage SPSCK MOSI MISO Coolant Temp Air Temperature To Powertrain Control Module From Powertrain Control Module PTA 2 From PRNDL Switch 3 PTA 1 From PRNDL Switch 2 PTA 0 From PRNDL Switch 1 Appendix B: System Development Example MTT 48 V 2. 1 B - 6

POWER ON RESET At Reset, the following occurs • All registers set to initial default values • Interrupts are disabled • Stack Pointer set to $00 FF • Program Counter load with value at $FFFE $FFFF • Program execution begins Appendix B: System Development Example MTT 48 V 2. 1 B - 7

CPU INITIALIZATION Set proper bus frequency of 8 MHz • Configure CGM for proper bus frequency – Must use PLL, N = 8, L = 6 – See CGM exercise May wish to move stack location • Example: Move stack to address $0100 LDHX #$0101 TXS ; Subtracts 1 in process Initialize/clear RAM to known state • Could be performed using DMA – See DMA exercise part 4 Appendix B: System Development Example MTT 48 V 2. 1 B - 8

CPU INITIALIZATION If using interrupts • Initialize interrupt service routines – TIM Channel 1 – SCI Transmit and Receive – SPI Transmit and Receive – IRQ 2 Enable interrupts Appendix B: System Development Example MTT 48 V 2. 1 B - 9

I/O PORT INITIALIZATION NOTE: Order of submodule initialization may or may not be critical to application Configure I/O Ports • PRNDL – Set Port A Data Direction Bits 2 0 as inputs (default) • A/D Slave Select Line – Set Port A Data Bit 7 to 1 to disable SS line – Set Port A Data Direction Bit 7 as an output • Warning lamps – Write $00 to Port B Data register to deactivate warning lamps – Set all Port B Data Direction bits to outputs Appendix B: System Development Example MTT 48 V 2. 1 B - 10

SPI MODULE INITIALIZATION Configure SPI module • Select Master mode, polarity, phase and baud rate – SPMSTR bit = 1 – CPOL, CPHA = 01 Idle low, Read data on 2 nd clock edge – SPR 1: SPR 0 = 10 Baud rate of 250 KHz (8 MHz bus) • Turn on SPI – Set SPE bit in SPI Control register • Interrupts – Enable interrupts as required by application • SPIE bit for transmission complete interrupt (SPIF) • TDIE bit for transmit register empty interrupt (TDRE) Appendix B: System Development Example MTT 48 V 2. 1 B - 11

SCI MODULE INITIALIZATION Configure SCI module to communicate with Powertrain Control Module • Select number of data bits, parity, and baud rate – M = 0 8 data bits – PEN, PTY = 0 X Parity disabled, Parity Type is don’t care – SCP 1: SCP 0 = 01 Prescaling of 3 – SCR 2: SCR 1: SCR 0 = 001 Divisor of 2 9600 baud from 4 MHz external crystal frequency • Turn on SCI – Set ENSCI bit in SCI Control Register 1 • Interrupts – Enable interrupts as required by application • TCIE bit for transmission complete interrupt (TC) • TIE bit for transmit register empty interrupt (TDRE) • RIE bit for data received interrupt (RDRF) • Error interrupts (OR, NF, FE, PE) Appendix B: System Development Example MTT 48 V 2. 1 B - 12

TIM INITIALIZATION Initialize TIM module for measuring wheel speed reference pulse frequency • Configure prescaler value smallest resolution – PS 2: PS 1: PS 0 = 000 System clock ÷ 1 (default) • Resolution = 125 ns at 8 MHz bus clock • Configure channel 1 for input capture on rising edge – MS 1 A = 0 Input capture – ELS 1 B: ELS 1 A = 01 Rising edge detection • Interrupt as needed by application – Set CH 1 E bit for interrupt generation on capture • Enable Timer – Clear TSTOP bit in Timer Control Register Appendix B: System Development Example MTT 48 V 2. 1 B - 13

ADDITIONAL INITIALIZATION Initialize any RAM locations as required by application Begin Program execution Appendix B: System Development Example MTT 48 V 2. 1 B - 14

OPTIONAL INITIALIZATION Configure DMA module as needed by application • Could use DMA to service SCI or SPI interrupts • Set channel source and destination register addresses • Set up register • Set up Source/Destination address calculation – Interrupt source – Byte/Word Count • Enable channel in DMA Control Register 1 (DC 1) – Set Channel enable bit • Interrupt on complete of transfer – Set Channel interrupt enable bit in DC 1 Appendix B: System Development Example MTT 48 V 2. 1 B - 15

OPTIONAL INITIALIZATION Enable COP module • Clear COPD bit MOR register – Must be done at EPROM programming time Enable LVI module • Set LVIPWR bit in LVI Status and Control register • Enable Reset Generation if desired – Set LVIRST bit • Lock LVI – Set LVILCK bit to write protect register – Think low power modes Appendix B: System Development Example MTT 48 V 2. 1 B - 16

ADDITIONAL SYSTEM CONFIGURATION Before executing WAIT or STOP configure XIRQ module • Enable IRQ 2 interrupt • Clear IMASK 2 in IRQ Status and Control register Appendix B: System Development Example MTT 48 V 2. 1 B - 17

SYSTEM CONFIGURATION EXAMPLE Questions and Answers Appendix B: System Development Example MTT 48 V 2. 1 B - 18