ANDORINVERT ANDORINVERT AOI n n ANDNOR NANDAND AOI

AND-OR-INVERT電路 AND-OR-INVERT (AOI) 電路: n n AND-NOR = NAND-AND = AOI電路 (和項積表示) E. g. F = (AB+CD+E)‘ 以線結-AND邏輯閘表示: 先以 F‘ = AB+CD+E (積項和)表示，再求補數 F OR-反相 反相-AND Digital Circuits 3 -3

OR-AND-INVERT電路 OR-AND-INVERT (OAI)電路 n n OR-NAND = NOR-OR = OAI (積項和表示) F = ((A+B)(C+D)E)'以線結-OR邏輯閘表示: 先以F' = (A+B)(C+D)E (和項積)表示，再求補數 F AND-反相 反相-OR Digital Circuits 3 -4

列表總論與舉例說明 Digital Circuits 3 -5

互斥-OR函數 n 互斥-OR函數[Exclusive-OR (XOR)]: 奇函數 x y = xy'+x'y 互斥-NOR (XNOR) (equivalence): 偶函數 l (x y)' = xy + x'y' 一些恆等式應用在XOR l x 0 = x l x 1 = x' l x x = 0 l x x' = 1 l x y' = (x y)' l x' y = (x y)' 交換性與結合性 l A B = B A l (A B) C = A (B C) = A B C l n n n Digital Circuits 3 -8

互斥-OR函數 電路實現: n (x'+y')x + (x'+y')y = xy'+x'y = x y x y = xy'+x'y ∵反相-OR=AND-反相 Digital Circuits 3 -9

四變數互斥-OR函數 A B C D=(A B) (C D ) =(AB’+A’B) (CD’+C’D) =(AB’+A’B)(CD+C’D’)+(AB+A’B’)(CD’+C’D ) = Σ(1, 2, 4, 7, 8, 11, 13, 14) Digital Circuits 3 -12

A Top-Down Design Flow Specification RTL design and Simulation Logic Synthesis Gate Level Simulation ASIC Layout FPGA Implementation Digital Circuits 3 -18

模組宣告 n 關鍵字範例： module, end-module, input, output, wire, and, or, 與 not. HDL範例3 -1 Digital Circuits 3 -19

HDL範例 3. 1 n 圖 3 -37電路的HDL描述 例證後的模組 Digital Circuits 3 -20

閘延遲 (範例3 -1) Digital Circuits 3 -22

HDL範例 3. 1 的模擬輸出 Digital Circuits 3 -24

HDL範例 3. 4 Digital Circuits 3 -26

HDL範例 3. 5 (續) Digital Circuits 3 -29

Digital Circuits 3 -30