Analyzing Reconvergent Fanouts in Gate Delay Fault Simulation

Analyzing Reconvergent Fanouts in Gate Delay Fault Simulation Hillary Grimes & Vishwani D. Agrawal Dept. of ECE, Auburn University Auburn, AL 36849 1

Outline • Problem Statement • Reconvergent Fanout Analysis ØAmbiguity Lists • Fault Detection ØDetection Threshold ØDetection Gap • Results • Conclusion 2

Definitions • Gate Delay Fault Model ØAssume that a delay fault is lumped at a single faulty gate • Detection Threshold ØMinimum size delay fault that is guaranteed to be detected by the test • Detection Gap ØRelates the detection threshold to the slack at the fault site 3

Problem Statement • When signals produced by a common fanout point reconverge, the inputs to the reconvergent gate are correlated • Conventional simulation ignores this correlation when bounded gate delays are used ØProduces pessimistic results in both bounded delay simulation and gate delay fault simulation 4

Bounded Delay Simulation 0 1 3 1, 2 3 5 4 1, 2 2 1 11 5 1 1, 3 3, 4 5 9 5

Reconvergent Fanout Analysis Fall occurs at time ‘x’ 0 Hazard cannot occur 1 x 3 1, 2 3 5 4 1, 2 6 11 1, 2 x+1 5 1 1 3, 4 1, 3 Output rises at least 1 unit after ‘x’ 5 9 6

Ambiguity Lists • Ambiguity Lists generated at fanout points contain Øoriginating fanout name Øambiguity interval – min and max delays from fanout to gate • Ambiguity list propagation is similar to fault list propagation in concurrent fault simulation 7

Ambiguity List Propagation • Ambiguity lists at the inputs of a reconvergent gate help determine its output ØIf signal correlations are such that no hazard can occur, the hazard is suppressed ØOtherwise, the ambiguity lists are propagated to the gate’s output, and ambiguity intervals are updated 10/25/2007 ITC-07 Paper 26. 3 8

Ambiguity List Propagation • Bounded Delay Simulation ØAmbiguity lists propagated through every gate • Detection Threshold Evaluation ØAmbiguity Lists propagated through downcone of the fault site 10/25/2007 ITC-07 Paper 26. 3 9

Detection Threshold Ts = 12 Det. Threshold = 8 0 1, 3 1, 2 3 5 4 1, 2 1 1 1, 3 2 5 6 11 1, 2 Corrected Det. Threshold = 6 3, 4 5 9 10

Detection Gap for a Gate PI p 1 - longest delay path through gate Gate p 2 PO Ts p 1 delay p 2 delay slack t gap DT(p 2) • Ideal gate delay test should activate longest path p 1, detection threshold = slack, gap = 0 • A test that activates path p 2, p 2 < p 1, gap = detection threshold – slack • Smaller the gap, better is the test 11

Results • ISCAS 85 benchmark circuits simulated with 10, 000 random vectors • Simple wireload model ØBounded delays set to (3. 5 n ± 14%), where n is the number of fanouts Program can accept any available gate delay data, which may be normally available from process technology characterization 12

Results: Fault-Free Simulation Circuit Without Reconvergent Fanout Analysis With Reconvergent Fanout Analysis Largest EA Largest LS c 3540 96. 0 204. 0 121. 6 196. 8 C 5315 76. 8 204. 0 91. 2 194. 4 C 6288 158. 4 576. 0 236. 8 504. 0 C 7552 91. 2 204. 0 104. 0 201. 6 • Using reconvergent fanout analysis generally results in larger EA and smaller LS values at outputs • More apparent for circuits that contain a large number of reconvergent fanouts, such as in multiplier circuit c 6288 13

Results: Fault Simulation • Average detection gap and fault coverage of faults detected with gap ≤ 3. 5 recorded • For fault coverage, faults are counted as detected if they are detected: ØThrough the longest path through the gate ØThrough a path which is shorter than longest path by only one gate delay 14

Results: Fault Simulation Without Reconvergent Fanout Analysis Circuit c 432 c 499 c 880 c 1355 c 1908 c 2670 c 3540 c 5315 c 7552 Average Detection Gap 110. 4 51. 7 16. 4 50. 8 55. 2 41. 8 50. 4 21. 7 39. 4 Faults Detected with Gap ≤ 3. 5 7. 35% 4. 91% 48. 41% 4. 80% 21. 70% 31. 25% 32. 60% 55. 72% 13. 43% With Reconvergent Fanout Analysis Average Detection Gap 108. 9 44. 0 12. 9 42. 2 47. 1 36. 0 44. 0 6. 1 22. 5 Faults Detected with Gap ≤ 3. 5 7. 08% 12. 85% 48. 86% 13. 62% 25. 10% 36. 54% 33. 19% 57. 31% 22. 83% 15

Conclusion • When reconvergent fanout analysis is used, gate delay fault simulation results are less pessimistic • During simulation, ambiguity lists can grow quite large ØEfficiency in list propagation needs to be improved • This min-max delay simulator has found application in hazard-free delay test generation 16