AnalogtoDigital Conversion Terminology analog continuously valued signal such

Analog-to-Digital Conversion Terminology analog: continuously valued signal, such as temperature or speed, with infinite possible values in between digital: discretely valued signal, such as integers, encoded in binary analog-to-digital converter: ADC, A/D, A 2 D; converts an analog signal to a digital signal digital-to-analog converter: DAC, D/A, D 2 A An embedded system’s surroundings typically involve many analog signals.

7. 0 V 6. 5 V 6. 0 V 5. 5 V 5. 0 V 4. 5 V 4. 0 V 3. 5 V 3. 0 V 2. 5 V 2. 0 V 1. 5 V 1. 0 V 0. 5 V 0 V 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 proportionality 4 4 3 3 analog output (V) Vmax = 7. 5 V analog input (V) Analog-to-digital converters 2 1 t 1 0100 t 2 t 3 t 4 2 1 time 0110 0101 Digital output analog to digital Embedded Systems Design: A Unified Hardware/Software Introduction, (c) 2000 Vahid/Givargis t 1 t 2 0100 t 3 1000 0110 Digital input digital to analog t 4 time 0101

Proportional Signals Simple Equation Vmax Assume minimum voltage of 0 V. Vmax = maximum voltage of the analog signal a = analog value n = number of bits for digital encoding 1. . 1 = 2 n-1 … 2 n = number of digital codes M = number of steps, either 2 n or 2 n – 1 d = digital encoding a / Vmax = d / M 0 V 0. . 0 = 0

Resolution Let n = 2 Vmax 3=11 M = 2 n – 1 r 3 steps on the digital scale d 0 = 0 b 00 d. Vmax = 3 = 0 b 11 3=11 2=10 M = 2 n 2=10 4 steps on the digital scale d 0 = 0 b 00 d. Vmax - r = 3 = 0 b 11 (no d. Vmax ) r, resolution: smallest analog change resulting from changing one bit 1=01 0 V 0=00

DAC vs. ADC DAC: n digital inputs for digital encoding d analog input for Vmax analog output a x 0 x 1 … Vmax DAC Xn-1 ADC: Given a Vmax analog input and an analog input a, how does the converter know what binary value to assign to d in order to satisfy the ratio? – – – may use DAC to generate analog values for comparison with a ADC “guesses” an encoding d, then checks its guess by inputting d into the DAC and comparing the generated analog output a’ with original analog input a How does the ADC guess the correct encoding? a

ADC: Digital Encoding Guessing the encoding is similar to finding an item in a list. 1. Sequential search – counting up: start with an encoding of 0, then 1, then 2, etc. until find a match. • 2 n comparisons: Slow! 2. Binary search – successive approximation: start with an encoding for half of maximum; then compare analog result with original analog input; if result is greater (less) than the original, set the new encoding to halfway between this one and the minimum (maximum); continue dividing encoding range in half until the compared voltages are equal • n comparisons: Faster, but more complex converter Takes time to guess the encoding: start conversion input, conversion complete output

ADC using successive approximation • Given an analog input signal whose voltage should range from 0 to 15 volts, and an 8 -bit digital encoding, calculate the correct encoding for 5 volts. Then trace the successive-approximation approach to find the correct encoding. • Assume M = 2 n – 1 a / Vmax = d / M 5 / 15 = d / (256 - 1) d = 85 or binary 0101

ADC using successive approximation Step 1 -4: determine bits 0 -3 ½(Vmax – Vmin) = 7. 5 volts Vmax = 7. 5 volts. 0 0 0 0 ½(7. 5 + 0) = 3. 75 volts Vmin = 3. 75 volts. 0 1 0 0 0 ½(7. 5 + 3. 75) = 5. 63 volts Vmax = 5. 63 volts 0 1 0 0 0 ½(5. 63 + 3. 75) = 4. 69 volts Vmin = 4. 69 volts. 0 1 0 0 Embedded Systems Design: A Unified Hardware/Software Introduction, (c) 2000 Vahid/Givargis

ADC using successive approximation Step 5 -8: Determine bits 4 -7 ½(5. 63 + 4. 69) = 5. 16 volts Vmax = 5. 16 volts. 0 1 0 0 ½(5. 16 + 4. 69) = 4. 93 volts Vmin = 4. 93 volts. 0 1 0 1 0 0 ½(5. 16 + 4. 93) = 5. 05 volts Vmax = 5. 05 volts. 0 1 0 1 0 0 ½(5. 05 + 4. 93) = 4. 99 volts 0 1 0 1 Embedded Systems Design: A Unified Hardware/Software Introduction, (c) 2000 Vahid/Givargis

Constructing ADC Analog input Vmax Vmin Comparator State machine Timing control DAC SAR BUF SAR: Successive approximation register Digital output

Bit Weight Notice the concept of bit weight in the last example: bit 7 = 7. 5 V = 15/2 bit 6 = 3. 75 V = 15/4 Digital Bit Weight (V) 7 10/2 = 5 6 10/4 = 2. 5 Each bit is weighted with an analog value, such that a 1 in that bit position adds its analog value to the total analog value represented by the digital encoding. 5 10/8 = 1. 25 4 10/16 = 0. 625 3 10/32 = 0. 313 2 10/64 = 0. 157 Example: -5 V to +5 V analog range, n=8 1 10/128 = 0. 078 0 10/256 = 0. 039

Bit Weight Example (continued): -5 V to +5 V analog range, n=8 Digital numbers for a few analog values – – Values shown increment by 6 bits (weight for bit position 5 is 1. 25 V) Maximum digital number only approximates the maximum analog value in the range • Try (-5) + sum of all bit weights Analog (V) Digital (hex) -5 00 -3. 75 20 -2. 5 40 -1. 25 60 0 80 1. 25 A 0 2. 5 C 0 3. 75 E 0 5 -0. 039 = 4. 961 FF

Terms & Equations Offset: minimum analog value Span (or Range): difference between maximum and minimum analog values Max - Min n: number of bits in digital code (sometimes referred to as n-bit resolution) Bit Weight: analog value corresponding to a bit in the digital number Step Size (or Resolution): smallest analog change resulting from changing one bit in the digital number, or the analog difference between two consecutive digital numbers; also the bit weight of the Span / 2 n (Assume M = 2 n) Let AV be Analog Value; DN be Digital Number: AV = DN * Step Size + Offset = (DN / 2 n )* Span + Offset DN = (AV - Offset) / Step Size = (AV - Offset) * 2 n / Span

MPC 555 QADC 64 - Queued Analog to Digital Converter Module-64 • 16 analog channels via internal multiplexing • 10 -bit ADC resolution • Converts voltage to an integer value (0 -1023) • Polling or interrupt driven • Programmable channels AN 0 -ANx

MPC 555 QADC 64

MPC 555 QADC 64 CCW Table CCW 0 CCW 1 AN 0 AN 1 AN 2 AN 3 … CCW 63 ADC A CCW tells the ADC which channel to scan and how long to sample the signal. QACR 1: start a scan by setting SSE bit QASR 0: CF flag is set after conv is done Result Table Result 0 A Result is stored for Result 1 each scan of a channel when the conversion is … complete. Result 63

Scan Sequence and Conversion • After the ADC is initialized, a sequence of scans is set up as a “queue” in the CCW Table. • Each channel to be scanned is added to the queue at successive positions 0, 1, 2, etc. For example: CCW 0, CCW 1, CCW 2, CCW 3. – An end-of-queue marker should be added at the next position. • The ADC starts the scan and conversion when it is triggered by the enable bit. • The ADC reads the CCWs, one after another until end-of-queue is reached, and for each CCW, it converts the signal on the specified channel. – A conversion on a channel stores a result in the respective position of the Result Table, e. g. , the result for CCW 0 is stored at Result 0, etc. • When the scan and conversion is complete for all CCWs, then the ADC sets the completion flag to 1. Now all digital results are available to be read from the Result Table.

QADC Interface • Programmability using a queue – Scan a few channels quickly – Scan a channel multiple times – Scan large number of channels • QACR 1 – QADC 64 Control Register 1 o 16 bit register at 0 x 30480 C o SSE 1 – bit 2 – Single Scan enable (bit 0 is MSb) o MQ 1 – bits 3 -7 o Set to binary 00001 to identify Queue 1 • QASR 0 – QADC 64 Status Register 0 o 16 bit register at 0 x 304810 o ADC sets a flag when the conversion is done o CF 1 – bit 0 – Conversion Complete flag (bit 0 is MSb)

QADC Interface • CCW Table o table of Conversion Command Words, where each command word specifies how to perform a scan/conversion operation for an input channel o CCW: 16 bit command word, starting at address 0 x 304 A 00 o A queue is a scan sequence of one or more input channels. o A queue is started by a trigger event, which is a way to cause the QADC 64 to begin executing the command words. o Each CCW requests the conversion of an analog channel to a digital result. The CCW specifies the analog channel number, the input sample time, and whether the queue is to pause after the current CCW.

QADC Interface • Total conversion time: initial sample time, final sample time, and resolution time o Initial sample time – time during which the selected input channel is driven by the buffer amplifier onto the sample capacitor (disabled by means of the BYP bit in the CCW) o Final sampling period – time to set up DAC array o Resolution period – time to convert voltage in the DAC array to a digital value

QADC Interface • Result Word Table o table of Result Words, where each result word is the digital result of a conversion o Results from a sequence of conversions are placed in the Result Word Table. o RW: 16 bit result word, starting at address 0 x 304 A 80 • Programming the QADC: – Reset the ADC queue – Add (to the queue) each analog input channel to be scanned; e. g. , four channels, 0 through 3 (AN 0 -AN 3) – Add an end-of-queue marker to terminate the scan sequence – Start a conversion on the ADC, which begins reading each analog input and converting it to a digital value

QADC 64 Memory-mapping Layout Bit 0 Bit 15 0 x 30 4800 Module Config. Reg. 0 x 30 4802 Test Reg. 0 x 30 4804 Interrupt Reg. 0 x 30 4806 Port A Data Port B Data 0 x 30 4808 Port A Direction Reg. 0 x 30 4 A 00 0 x 30 480 A 0 x 30 480 C 0 x 30 480 E 0 x 30 4810 0 x 30 4812 0 x 30 4 A 80 Control Reg. 1 Control Reg. 2 Status Reg. 0 Status Reg. 1 64 -entry 16 -bit Conversion Command Word Table (Configurable: one queue or two queues) 0 x 30 4 A 7 E 64 -entry 16 -bit Result Word Table 64 -entry, 16 -bit 0 x 30 4 AFE The above is the memory-mapping for the 1 st QADC 64. The 2 nd QADC 64 using different starting addresses.

Programming QADC 64 CCW Format: 6 P 7 BYP 8 9 10 11 12 12 14 15 IST CHAN Example: Write a CCW into CCW table to scan channel n. Channel with no amplifier bypassing and 4 -cycle initial sample time (16 cycles in total). n. Queue. Val = *(p. CCWTable n. Channel; n. Queue. Val & 0 x. FF 3 F; n. Queue. Val | 0 x 0040; + n. Queue) = n. Queue. Val;

The Control Registers

The Status Registers CF 1 Queue 1 completion flag PF 1 Queue 1 pause flag TOR 1 Trigger over-run QS Queue status CWP Command word pointer

Programming the ADC • Initialize the QADC: reset queue to be empty; set up interrupt driven mode, interrupt levels, clock rate. • Write into the command word queue (a sequence of A to D conversion commands). • In software triggered mode, initiate the conversion by writing into QACR[SSE] bit. • Monitor the conversion finished flag (CF). • Read the results, and reset CF and PF flags.

Programming QADC 64 Example: Reset QADC 64 by writing END-OF-QUEUE (63 in decimal) as the first word of CCW table. void QADCR 64_Reset() { g_n. Num. Channels = 0; QADCR 64_Set. Queue(0, QADCR 64_END_QUEUE, QADCR 64_QCKL_MAX); } QADCR 64_Set. Queue: Given CCW entry index, CCW channel/end-ofqueue command, and final sample setting, write the corresponding CCW.

Programming QADC 64 Example: Start scanning in polling mode (interrupt disabled) – Set up control register 1 void QADCR 64_Start_Convert_Poll () { unsigned short * p. QACR 1; p. QACR 1 = (unsigned short *) 0 x 30480 C; // Bit 0 CIE 1 Conversion Interrupt Enable 0 // Bit 1 PIE 1 Pause Interrupt Enable 0 // Bit 2 SSE 1 Single Scan Enable 1 // MQ=00001; software triggered single scan mode *p. QACR 1 = 0 x 2100; }

Programming QADC 64 Example: Determine if all conversions has finished – Checking status register 0 unsigned short QADCR 64_Is_Done() { unsigned short * p. QASR 0; unsigned short n. Result; p. QASR 0 = (unsigned short *) 0 x 304810; n. Result = (*p. QASR 0 & 0 x 8000); return n. Result; }

QADC Interrupt Sources

QADC 64 Interrupt Programming Set up interrupt register (0 x 304804 for 1 st QADC) 0 45 IRL 1 9 10 IRL 2 15 Reserved • IRL 1, IRL 2: interrupt levels for queue 1 and queue 2, respectively. • 5 -bit interrupt level: QADC 64 is IMB 3 device with interrupt level 0 -31 (stored in UIPEND). • Interrupt is generated at the completion of a CCW if it is the end of queue or has the pause bit set.