Analog Layout Figures Baker Li Boyce 1998 Ben

Analog Layout Figures ©Baker, Li, & Boyce 1998 Ben Blalock - 1 Analog Layout – Fall 2002 Electrical & Computer Engineering

Analog Layout • MOSFET Layout Ø layout example (with schematic): Figures ©Baker, Li, & Boyce 1998 Ben Blalock - 2 Analog Layout – Fall 2002 Electrical & Computer Engineering

Analog Layout • CMOS Passive Elements Ø Poly 1 -poly 2 capacitor structure Figures ©Baker, Li, & Boyce 1998 Ben Blalock - 3 Analog Layout – Fall 2002 Electrical & Computer Engineering

Analog Layout • CMOS Passive Elements Ø Parasitics associated with the poly 1 -poly 2 capacitor structure Figures ©Baker, Li, & Boyce 1998 Ben Blalock - 4 Analog Layout – Fall 2002 Electrical & Computer Engineering

Analog Layout • CMOS Passive Elements Ø Careful layout can reduce parasitic resistance associated with cap structure Figures ©Baker, Li, & Boyce 1998 Ben Blalock - 5 Analog Layout – Fall 2002 Electrical & Computer Engineering

Analog Layout • CMOS Passive Elements Ø Additional options for implementing capacitors in CMOS technology include: ® metal 1 -metal 2 capacitors ® MOS caps (drain shorted to source MOSFET operating in SI) ® n+ or p+ diffusions to well or substrate Ø Well-to-substrate Figures ©Baker, Li, & Boyce 1998 Ben Blalock - 6 Analog Layout – Fall 2002 Electrical & Computer Engineering

Analog Layout • CMOS Passive Elements Ø Good analog design utilizes ratioing of components: Figures ©Baker, Li, & Boyce 1998 Ben Blalock - 7 Analog Layout – Fall 2002 Electrical & Computer Engineering

Analog Layout • CMOS Passive Elements Ø Guard ring components to isolate them from substrate noise: Figures ©Baker, Li, & Boyce 1998 Ben Blalock - 8 Analog Layout – Fall 2002 Electrical & Computer Engineering

Analog Layout • CMOS Passive Elements Ø Good example of layout of matched elements (R 1 & R 2): ® consistent orientation (horizontal in this case) ® consistent parasitics ® don’t forget to guard ring! Figures ©Baker, Li, & Boyce 1998 Ben Blalock - 9 Analog Layout – Fall 2002 Electrical & Computer Engineering

Analog Layout • CMOS Passive Elements Ø Common-centroid layout improves element matching (at the expense of uneven parasitics between the elements): ® in Fig. 7. 7(a), RA = ‘ 16’ and RB = ‘ 20’ ® in Fig. 7. 7(b), RA = ‘ 18’ and RB = ‘ 18’ Figures ©Baker, Li, & Boyce 1998 Ben Blalock - 10 Analog Layout – Fall 2002 Electrical & Computer Engineering

Analog Layout • Common-centroid structure for four elements (resistors, MOSFETs, or capacitors): Figures ©Baker, Li, & Boyce 1998 Ben Blalock - 11 Analog Layout – Fall 2002 Electrical & Computer Engineering

Analog Layout • Also use dummy elements to improve matching: Figures ©Baker, Li, & Boyce 1998 Ben Blalock - 12 Analog Layout – Fall 2002 Electrical & Computer Engineering

Analog Layout • Beware of poly under etching in layout of capacitor unit cells! Ø Circular poly structures guarantee consistent under etching: Figures ©Baker, Li, & Boyce 1998 Ben Blalock - 13 Analog Layout – Fall 2002 Electrical & Computer Engineering

Analog Layout Good layout practices for analog circuits: • Use gate lengths several times larger than the technology’s minimum gate length if all possible. This helps reduces effects while improving matching. • Use multiple source/drain contacts along the width of the transistor to reduce parasitic resistance and provides evenly distributed current through the device. Figures ©Baker, Li, & Boyce 1998 Ben Blalock - 14 Analog Layout – Fall 2002 Electrical & Computer Engineering

Analog Layout Good layout practices for analog circuits (continued): • Interdigitize large aspect ratio devices to reduce source/drain depletion capacitance. Using an even number (n) of gate fingers can reduce Cdb, Csb by one-half or (n + 2)/2 n depending on source/drain designation. Typically it is preferred to reduce drain capacitance more so than source capacitance. Also use dummy poly strips to minimize mismatch induced by etch undercutting during fab. Figures ©Baker, Li, & Boyce 1998 Ben Blalock - 15 Analog Layout – Fall 2002 Electrical & Computer Engineering

Analog Layout Good layout practices for analog circuits (continued): • Matched devices should have identical orientation. An example of what not to do is shown below. Figures ©Baker, Li, & Boyce 1998 Ben Blalock - 16 Analog Layout – Fall 2002 Electrical & Computer Engineering

Analog Layout Good layout practices for analog circuits (continued): • Interdigitization can be used in a multiple transistor circuit layout to distribute process gradients across the circuit. This improves matching. • Use common-centroid structures. Figures ©Baker, Li, & Boyce 1998 Ben Blalock - 17 Analog Layout – Fall 2002 Electrical & Computer Engineering

Analog Layout Matching Errors in MOSFET Current Mirrors: • Good layout design is essential for circuits needing matched devices. • Layout techniques are effectively used to minimize first-order mismatch errors due to variations in these process parameters: gate-oxide thickness, lateral diffusion, oxide encroachment, and oxide charge density. Figures ©Baker, Li, & Boyce 1998 Ben Blalock - 18 Analog Layout – Fall 2002 Electrical & Computer Engineering

Analog Layout Matching Errors in MOSFET Current Mirrors (continued): • Considering only the effects of threshold voltage mismatch within the simple current mirror, its current ratio is described by for SI saturation operation if a symmetric distribution in threshold voltage across the circuit is assumed (i. e. , VTHN 1 = VTHN 0. 5 VTHN and VTHN 2 = VTHN + 0. 5 VTHN). Note the dependence on VGS. A reduction in VGS increases the input/output error in current mirrors induced by threshold voltage mismatch. Figures ©Baker, Li, & Boyce 1998 Ben Blalock - 19 Analog Layout – Fall 2002 Electrical & Computer Engineering

Analog Layout Matching Errors in MOSFET Current Mirrors (continued): • Considering only transconductance parameter mismatch, where the value of KPn is the average transconductance parameter between the two transistors within the simple current mirror. • Considering only VDS and effects [SI sat. ] , These, too, can be a significant source of error (e. g. , 11%! if VDS 1 = 2 V, VDS 2 = 4 V, ( c + m)1 = 0. 04 V-1, and ( c + m)1 = 0. 05 V-1). Figures ©Baker, Li, & Boyce 1998 Ben Blalock - 20 Analog Layout – Fall 2002 Electrical & Computer Engineering