Analog Device Chipsets Featured In New Mobile Phones
Analog Device Chipsets Featured In New Mobile Phones Eric Tong April 6, 2004
Agenda n Background n AD 20 msp 430 Soft. Fone® Chipset n Digital Baseband Controller - AD 6526 n ADSP-2181 n Why ADSP-2181 Not ADSP-21061 n Question
Background n December 15, 2003 – Analog Devices joint development with TCL Mobile Communication Co. , Ltd. on GSM mobile phones n Why TCL Mobile Communication CO. – Population • 1. 3 billion in China • 28 million in Shanghai and Beijing – TCL Customer • 9. 8 Million in 2003 • 100. 8 Million US Dollars Net Profit in 2003
AD 20 msp 430 Soft. Fone® Chipset n Analog Devices’ Fourth Generation GSM Base. Band Chipset – Color Displays, Camera, Games, and Polyphonic Ring Tones n Consists Two Chips – Digital Baseband Controller • AD 6522, AD 6526, AD 6528 – Analog/Mixed-Signal Interface Chip • AD 6521, AD 6535
AD 6526 Description Second Device of the AD 20 msp 430 series of Soft. Fone® GSM Baseband Processors n Designed to be n – fully integrated – easy to use – compatible with GSM 900, DCS 1800 and PCS 1900 handsets – Direct PC data Interface n Includes – Analog Devices ADSP-218 X DSP core – ARM® Controller
AD 6526 Functional Block Diagram 16 -bit Fixed Point Processor n Data and Program SRAM n Speech Encoding / Decoding n Hardware Interface n – Radio – Keypad – Display n Operating Voltage Range 1. 7 -1. 9 V
ADSP-2181 Description n Singe-Chip Microcomputer Optimized for DSP n ADSP-2100 Family Base Architecture – – – – – ALU, MAC, Shifter Data Address Generators Program Sequences Two Serial Ports 16 -bit Internal DMA Port Byte DMA Port Programmer Timer Flag I/O Extensive Interrupt Capabilities
ADSP-2181 Block Diagram
ADSP-2181 (Parallel) n In One Processor Cycle, ADSP-2181 can – – – n Generate the Next Program Address Fetch the Next Instruction Perform One or Two Data Moves Update One or Two Data Address Pointers Perform a Computational Operation At the same time, the processor continues to – – Receive and transmit data through the two serial ports Receive and/or Transmit Data through the Internal DMA Port Receive and/or Transmit Data Through the Byte DMA Port Decrement Timer
ADSP-2181 Block Diagram
ADSP-2181 Data Transfer n Five Internal Buses 1. 2. 3. 4. 5. n Program Memory Address (PMA) Bus – 14 bits Data Memory Address (DMA) Bus – 14 bits Program Memory Data (PMD) Bus – 24 bits Date Memory Data (DMD) Bus – 16 bits Result (R) Bus – 16 bits 16 -bits Internal DMA Port
Why ADSP-2181 Not ADSP-21061 n Fast External Memory Access – – n External Address Bus External Data Bus Internal DMA Port Byte DMA Port Simultaneously Communication Port – Two 5 -bits Serial Port
Why ADSP-2181 Not ADSP-21061 n Parallel Operation – ADSP-21061 is designed for FIR filter – ADSP-2181 is designed for Signal Convolution n Power. Down Control Logic – Protect from Sudden High Signal Power n Other Features – Double Metal – Low Power (1. 7 V Vs 5. 0 V)
Why ADSP-2181 Not ADSP-21061 n Size
Why ADSP-2181 Not ADSP-21061
References: n n n http: //en. wikipedia. org/wiki/Shanghai#People_and_Culture http: //www. analog. com/Uploaded. Files/Data_Sheets/505104853 ADSP 2181_d. pdf http: //www. analog. com/Analog_Root/product. Page/product. Home /0%2 C 2121%2 CAD 20 MSP 430%2 C 00. html http: //www. analog. com/Uploaded. Files/Data_Sheets/280128552 AD 6526_pra. pdf http: //www. analog. com/Analog_Root/site. Page/press. Release. Ho me/0, 2145, Content. ID%253 D 29116%2526 aind%253 D%2526 La nguage%253 DEnglish%2526 resource. Web. Law. ID%253 D, 00. htm l http: //biz. yahoo. com/bw/040223/235640_1. html
References: http: //www. analog. com/processors/ep. Press. Release/0, 2458, leve l 4%253 D%25252 D 1%2526 Content. ID%253 D 27252%2526 level 1 %253 D 431%2526 level 2%253 D%25252 D 1%2526 level 3%253 D %25252 D 1%2526 resource. Web. Law. ID%253 D 36, 00. html n http: //www. analog. com/Analog_Root/product. Page/product. Home /0%2 C 2121%2 CAD 6522%2 C 00. html n http: //www. nokia. com/nokia/0, , 54665, 00. html n http: //www. analog. com/Uploaded. Files/Product_Briefs/12458878 8 ad 6526. pdf n
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