An Ultra Low Power Reconfigurable Task Processor for
An Ultra Low Power Reconfigurable Task Processor for Space Brian Smith, Greg Alkire – Pico. Dyne Inc. Wes Powell – NASA GSFC Greg Alkire/Brian Smith 1 197 MAPLD 2005
Outline • • • Project Overview Goals Architecture Implementation Approach Conclusion Greg Alkire/Brian Smith 2 197 MAPLD 2005
Project Overview • Phase II SBIR for Nano-Sat Computing • Proposed joining our existing FPGA work with a microcontroller on a single chip in Radiation Tolerant CMOS. • During Phase I, decided that Cool-RAD™ and a full 32 -bit processor would result in a more versatile chip. Greg Alkire/Brian Smith 3 197 MAPLD 2005
Project Goals • Combine RAMconfigurable logic array with a common processor and standard I/O Greg Alkire/Brian Smith 4 197 MAPLD 2005
Project Goals • FPGA of Suitable size for simple filters, state machines, and I/O protocol logic functions 48 x 48 Cell Logic Array Greg Alkire/Brian Smith 5 197 MAPLD 2005
Project Goals 32 -bit SPARC Leon 2 • Processor powerful enough for primary processor on Nano. Sat missions Greg Alkire/Brian Smith 6 197 MAPLD 2005
Project Goals • Radiation Tolerant and Low Power. Greg Alkire/Brian Smith • Pico. Dyne’s Cool. RAD™ process operates at 0. 5 V Core Voltage for low power, is very total dose hard, and uses Radiation Tolerant circuit design for low SEUs 7 197 MAPLD 2005
Implementation • 0. 35 um Cool-RAD™ • SEU tolerance achieved by using Single Event Resistant Topology (SERT) cell, developed by UNM/CAMBR and through adequate spacing of critical nodes Greg Alkire/Brian Smith 8 197 MAPLD 2005
Implementation • Cool-RAD™ • Low Power by using Ultra Low Power CMOS process developed under CULPRi. T program • Total Dose Tolerance of this process > 200 krad (Si) Greg Alkire/Brian Smith 9 197 MAPLD 2005
Processor • Leon 2 version of SPARC V 8 architecture with 5 stage pipeline. • Synthesized using STD Cell Library and standard tools. • Laid out for minimal delay to FPGA core & I/O Greg Alkire/Brian Smith 10 197 MAPLD 2005
Processor • Features: – 2 UARTS, interrupt driven – 16 bit programmable I/O – Interrupt Controller – 3 Timers (1 watchdog) – 8/16/32 bit memory controller – I-Cache – D-Cache Greg Alkire/Brian Smith 11 197 MAPLD 2005
FPGA • Basic logic block is a mux-based universal logic block • Implements 50 functions. Greg Alkire/Brian Smith 12 197 MAPLD 2005
FPGA • Input and output multiplexers route signal in and out of the logic section. • Each mux, for logic and routing, has it’s own configuration register Greg Alkire/Brian Smith 13 197 MAPLD 2005
FPGA • Fine-grain architecture • Each configuration register is accessible in memory map • The function of each logic and routing cell is configurable on-the-fly Greg Alkire/Brian Smith 14 197 MAPLD 2005
FPGA • • Hierarchical architecture First we developed individual logic cells Then built configuration logic Began placing adjacent cells and designing interconnect • Array is made up of some number of 16 x 16 cells Greg Alkire/Brian Smith 15 197 MAPLD 2005
FPGA • Created 4 x 4 blocks of cells • Then 16 x 16 • Configuration and routing take up very large percentage of die area Greg Alkire/Brian Smith 16 197 MAPLD 2005
RTP • FPGA placed on memory bus of LEON • I/O to die pads • FPGA configured through memory writes by processor software Greg Alkire/Brian Smith 17 197 MAPLD 2005
RTP • Development of user logic for array begins with HDL synthesis using std tools. • Layout done with custom tool-set Greg Alkire/Brian Smith 18 197 MAPLD 2005
RTP • Example designs include Filter implementation • (4 -pole CIC) • Synthesized, placed, routed, and simulated Greg Alkire/Brian Smith 19 197 MAPLD 2005
Potential Uses • Central Processor for nanosats • Data processor for miniaturized instruments • Embedded processor for subsystems • I/O, instrument interface, comm protocol Greg Alkire/Brian Smith 20 197 MAPLD 2005
Verification • FPGA verification performed via extraction and conversion to verilog netlist for simulation against original RTL testbench • Memory Cell verification two-fold basic functional via extraction and SPICE simulation • SPARC verification via IP test suites and focused implementation simulation. • RTP verification at interface level Greg Alkire/Brian Smith 21 197 MAPLD 2005
Conclusion • RTP will enable compression of board space for a computational node used in nanosats or as embedded or peripheral processor in larger spacecraft • Ultra Low Power implementation means less thermal noise to instruments, can be embedded closer to sensors Greg Alkire/Brian Smith 22 197 MAPLD 2005
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