An Embedded True Random Number Generator for FPGAs

An Embedded True Random Number Generator for FPGAs Paul Kohlbrenner Lockheed Martin 3201 Jermantown Road Fairfax, VA 22030, USA Paul. W. Kohlbrenner@lmco. com Kris Gaj George Mason University 4400 University Drive Fairfax, VA 22030, USA kgaj@gmu. edu Bebek, Jerry

• Random numbers are an essential in Com. S. …and, just as problematic. • There are several methods to generate them. • Unfortunately, all these methods are deterministic. The Question: HOW COULD A TOTALLY LOGICAL MACHINE GENERATE A RANDOM NUMBER?

The Answer: It The only truly random number sources are those related to Can’t. physical phenomena such as the rate of radioactive decay of an element or thermal noise of a semiconductor. BOTTOM LINE Randomness is bound to natural phenomena. It is impossible to algorithmically generate truly random numbers.

PSEUDO-VULNERABILITY Pseudo-Random numbers are prone to being broken into. . . and yes, it has happened. `It is not an impossible task to analyze patterns in pseudo-random numbers. A 40 -bit encryption with algorithmically generated random numbers could be broken in as little as 30 hours`. The Netscape 2. 0 Attack Was An

FPGA Advantage In The Field • Near-ASIC encryption speeds • Algorithm and resource efficiencies • In service algorithm modification • Low development costs • Parameter and algorithm eraser on intrusion detection

The Method: Clock Jitter is variations in the significant instants of a clock. Jitter is nondeterministic (random) Jitter may have many sources: • semiconductor noise • cross talk • Power supply variations • electro-magnetic fields Jitter may be characterized in several ways: • Period Jitter • Amplitude Jitter

Period Jitter (clock skew)

Overall Design

The Ring Oscillators Uses Propagation Delay – 130 MHz x 2

The Sampler One of the clock signals is used to sample the other signal.

The Output From The Sampler Clock Skew (jitter) in between two clock signals is used (e. g. sampled) to generate a totally random bit. Note that clock skew will never be uniform. Note that clock skew is NOT simple out-phase ness.

Jitter (detail)

Good Speed Ratios n n Ring oscillators with closely matched frequencies require that a desired speed ratio must be achieved. What factors affect this achievement? n Variation in CLB speed n n n 7% difference between the slowest CLB and the fastest one Sensitive to temperature and difficult for measurement Variation in the frequency of an oscillator with the chip temperature n n Close placement To use a large number of oscillators

Evidence of Jitter n n n Clocks with jitter lead to randomness of output bit stream If signal S 0 has a single length, the output will be deterministic (all 0 s, or 1 s or 0 s and 1 s with a repeating pattern) Evidence: Variation in the cycle lengths of Oscillators Variation in the cycle length of the signal S 0

Evidence of Jitter (details) Frequency 130 MHz

Bias in the Output n n Ideal Output: 1 s and 0 s are evenly and randomly distributed. Output with bias: 1 s more likely than 0 s, or vice versa The sources of bias: n n The limited number of difference bit length of S 0 signal Occasional meta-stable output from the sampling flip-flop, (using a buffer can alleviate this problem)

Reduction of Bias n XOR of successive pairs of bits Example: P(X=1)=2*p(1 -p), P(X=0)=p^2+(1 -p)^2 (p is the probability of 1 s) n A von Neumann corrector n NOTE: n n Limitation: no correlations in the output bit stream Disadvantage: reduction of the output bit rate

Output Bit generation speed

Experimental Environment n n SLAAC-1 V board with three Xilinx Virtex XCV 1000 FPGA Synplify V 7. 2 Xilinx ISE 4. 2 NIST Statistical Test Suite for Random and Pseudorandom Number Generator for Cryptographic Applications

Experimental Results P-value: the probability that a perfect random number generator would have produced a sequence less random than the sequence that was tested; The larger, the better.

Future Work n Increasing output bit rate by n n Increasing the speed of ring oscillators Generating S 0 signal from both rising and falling edge of the clock Increasing the number of oscillators to solve problems in finding matched CLBS Adding a counter to S 0 signal for real time “noisefailure” alarm

Conclusion n n The implementation is useful addition to the cryptographic systems using FPGA No special requirement within FPGA increases the universal of the design

Questions ? ? ?