An Efficient and Accurate DC Analysis Technique for

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An Efficient and Accurate DC Analysis Technique for Switched. Capacitor Circuits Gabor C. Temes

An Efficient and Accurate DC Analysis Technique for Switched. Capacitor Circuits Gabor C. Temes School of Electrical Engineering and Computer Science Oregon State University 12/4/2020 temes@eecs. oregonstate. edu 1/12

SC branch and DC model 12/4/2020 temes@eecs. oregonstate. edu 2/12

SC branch and DC model 12/4/2020 temes@eecs. oregonstate. edu 2/12

Power and Energy Relations • Power at input : • Total Energy drawn from

Power and Energy Relations • Power at input : • Total Energy drawn from input : • Change in energy stored in C : • Power lost in switches, independent of switch(Ron): 12/4/2020 temes@eecs. oregonstate. edu 3/12

Special Cases 12/4/2020 temes@eecs. oregonstate. edu 4/12

Special Cases 12/4/2020 temes@eecs. oregonstate. edu 4/12

SC Voltage-Doubler 12/4/2020 temes@eecs. oregonstate. edu 5/12

SC Voltage-Doubler 12/4/2020 temes@eecs. oregonstate. edu 5/12

DC model without Parasitics Power Efficiency 12/4/2020 temes@eecs. oregonstate. edu 6/12

DC model without Parasitics Power Efficiency 12/4/2020 temes@eecs. oregonstate. edu 6/12

DC model with Parasitics 12/4/2020 temes@eecs. oregonstate. edu 7/12

DC model with Parasitics 12/4/2020 temes@eecs. oregonstate. edu 7/12

Parameters with Stray Capacitances DC Parameters Vout Iin Iout Pin Pout η DC Model

Parameters with Stray Capacitances DC Parameters Vout Iin Iout Pin Pout η DC Model 9. 285 V 44. 29 A 10 A 221. 4 W 92. 86 W 42% HSPICE 9. 2226 V 45. 53 A 10. 15 A 227. 6 W 93. 64 W 41% Power efficiency is reduced due to the losses in parasitic 12/4/2020 temes@eecs. oregonstate. edu 8/12

Active Filter Stage (1/2) 12/4/2020 temes@eecs. oregonstate. edu 9/12

Active Filter Stage (1/2) 12/4/2020 temes@eecs. oregonstate. edu 9/12

Active Filter Stage (2/2) 12/4/2020 temes@eecs. oregonstate. edu 10/12

Active Filter Stage (2/2) 12/4/2020 temes@eecs. oregonstate. edu 10/12

Input CM Generated in SCF (2/2) If (VA-VC)avg=0, the virtual ground VD will be

Input CM Generated in SCF (2/2) If (VA-VC)avg=0, the virtual ground VD will be connected to VB=VCM by an Reg=T/C resistance. Leakage current I causes changes in bias, or in common-mode voltage. For fully differential circuits; 12/4/2020 temes@eecs. oregonstate. edu 11/12

Input CM Generated in SCF (1/2) 12/4/2020 temes@eecs. oregonstate. edu 12/12

Input CM Generated in SCF (1/2) 12/4/2020 temes@eecs. oregonstate. edu 12/12

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