An Effective DFM Strategy Requires Accurate Process and

An Effective DFM Strategy Requires Accurate Process and IP Pre-Characterization Carlo Guardiani, Massimo Bertoletti, Nicola Dragone, Marco Malcotti, and Patrick Mc. Namara PDF Solutions Inc. DAC 2005, Anaheim, CA

Technology Roadmap Challenges 45 nm q Lithography q Layout pattern 90 nm q Back-end integration q. Low-k q. CMP q Product ramp issues q. Yield vs. performance 65 nm q Lithography q OPC/PSM integr. w/ photo-window q Front-end/Transistor q Layout dependent performance q Parametric variation dependence q Immersion litho, q OPC/PSM integration w/ photo window q Front end/Transistor q New gate/oxide architectures q Reliability

The Evolution of Product Yields n Random defects are no longer the dominant yield loss mechanism – Yields are limited by design features

From Reactive to Proactive DFM: A Copernican Revolution… Yield Revolved Around Rules n Design rules guarantee yield!…well, not really… n …then recommended rules n …and opportunistic design data base post-processing to enforce them Yield Models are the driving force in the DFM universe n n Accurate Yield Models Characterized in Silicon Fully integrated in standard design tools and flows

Rule-based DFM? MUX 4 X 1 AFY_Y 1 - 20 tracks MUX 4 X 1 AFY_PMSY 4 - 21 tracks 25 FPB 32 FPB MUX 4 X 1 AFY_COY 4 - 25 tracks MUX 4 X 1 AFY 1_Y 16 - 27 tracks 19 20 FPB

Reactive vs. Proactive DFM Design Verification DRM SPICE IP lib. Design DFM & Manufacturing Verification Physical Floorplan Formal Design Synthesis Place&route Timing & SI DFM Optimizations DFM MDP sign-off Dummy Fill OPC/RET Mask Making Manufacturing Facility DFM & Manufacturing Design Verification DRM SPICE Physical Design Verification IP lib. Design Yield –aware Synthesis Formal Yield Aware Floorplan Yield-aware Statistical Place&route Timing & SI DFM MDP sign-off DFM Tuning Dummy Fill OPC/RET Mask Making

Proactive DFM n Designer access to process data is limited – – n DFM today is Reactive Increased design cycle time Risky design feature changes Misaligned mask GDSII and design database DFM needs to be Proactive – – Up-front accurate process characterization Occurring early in the design flow Model based IP characterization Manufacturable-by-construction designs

DFM characterization Of IP libraries Process FR (D 0, l) RANDOM Library GDS Litho Process Window Yield Extractions Design Attributes Process Margins and Litho calibration data Context Generation ACC Design SYSTEMATIC n n n Library GDS Golden OPC/RET Lithography Simulator. pdfm Characterize IP library for yield (. pdfm) – Extract design attributes of yield models – Include random, design systematic and litho effects New yield library view (. pdfm) Enable hierarchical large capacity DFM chip analysis Libra ry YIMP ACC . pdfm

Random Yield Loss: Physical Mechanisms Material opens Material shorts Type Random Yield Loss Mechanisms Active, poly and metal shorts and opens due to particle defects Contact and via opens due to formation defectivity

Random Yield Loss: Test Structures n Extract Metal layer open and short defectivity n Extract Metal layer open and short Defect Size Distribution (DSD)

Systematic Yield Loss: Physical Mechanisms Type Systematic Yield Loss Mechanisms Impact of micro/macro loading design rule marginalities Leakage from STI related stress Contact/via opens due to local neighborhood effects (e. g. pitch/hole size) Misalignment, line-ends/borders

Systematic Yield Loss: Test Structures Without Neighborhood With Neighborhood To Pad A To Pad B To Pad C M 1 STI N+ N+ PWL P+

Printability Yield Loss: Physical Mechanisms Type Systematic Yield Loss Mechanisms Poor contact coverage due to misalignment and defocus/pull back Poly/Metal shorts Material opens

Layout Metric Printability Yield Loss: Modeling De foc us Misalignment re osu Exp k as M r ro r E Yield Loss coverage

The. pdfm View n Library characterized to generate manufacturability view (. pdfm) – Random and design systematic yield – Litho process window n Using calibrated yield models Cell Characteristic Library View Lay out GDS Schematic P&R Footprint SPICE Netlist LEF Performance . lib Logic Function Verilog Power Noise n Multi-layer litho process window incorporated … … Manufacturability . p. DFM

Application: IP library DFM Quality Analysis Yield sensitivity analysis Cell FR Improvement (ppb) NAND 2 CELL COAO 3 BTC 2 NOR 2 XC_R 2 10 8 orig 6 Y 1 4 Y 2 2 Y 3 0 Y 4 -2 Y 5 -4 Y 6 -6 Poly Open Poly Short M 1 Open Process Corner n n M 1 Short Dominant Process Effect n AOI CELL n Poly Open Poly Short M 1 Open Process Corner M 1 Short Optimal design depends on process corner – Ex NAND 2: Y 5, Y 6, Y 1, Y 4 Best becomes worst at different process corner – Ex NAND 2: Y 1_m 1 opens vs. Y 1_m 1 shorts DFM Sensitivity depends on layout attributes – M 1 more sensitive than Poly Identify redundant layout implementations – Ex AOI: Y 4, Y 5

Yield aware synthesys and place&route VERIFICATION RTL Design Hierarchical Floorplan Physical Synthesis n Yield Gap Yield Estimator Estimation Models Yield Optimizer Optimization Extended DFM IP Chip Assembly Sign-off n DFM SW plug-ins. Yield View (. pdfm) LIBRARIES Standard Libraries Proactive DFM Maximize manufacturability by construction

Conclusions n Impact of design systematic and lithography yield loss mechanisms crossed over random phenomena n Rule-based, reactive DFM is impractical n Model-based, proactive DFM is the answer – Early in the design flow – Find the best trade-off based on actual process capabilities – Before verification