An automatic tool flow for the combined implementation

An automatic tool flow for the combined implementation of multi-mode circuits Brahim Al Farisi, Karel Bruneel, João Cardoso, Dirk Stroobandt

Overview • Multi-mode circuit • FPGA • Dynamic reconfiguration: • Modular dynamic reconfiguration (MDR) • Dynamic circuit specialization (DCS) • Novel tool flow • Experiments and results • Conclusions • Future work 1

Multi-mode circuit • Several circuits, called modes, that are used mutually exclusive in time • Example: software defined radio • Goal: Area efficient implementation through hardware resource sharing 2

FPGA 0 11 0 0 1 10 0 1 0 1 0 L U T 0 FF 0 1 0 0 1 3

Conventional FPGA tool flow • Input: textual description of functionality HDL design SYNTHESIS MAP LUT circuit PLACE ROUTE Configuration 4

Textual description: HDL design in 0 in 1 in 2 in 3 sel 0 out entity multiplexer is port( sel : in std_logic_vector(1 downto 0); in : in std_logic_vector(3 downto 0); out : out std_logic ); end multiplexer; architecture behavior of multiplexer is begin out <= in(conv_integer(sel)); end behavior; sel 1 5

Conventional FPGA tool flow HDL design SYNTHESIS • Input: Textual description of functionality • Internal representation: LUT circuit • Output: FPGA configuration MAP LUT circuit PLACE ROUTE Configuration 100101 011100 001111 6

Dynamic reconfiguration of FPGAs M 1 M 2 M 3 M 231 • Advantages: • Disadvantage: • Smaller area • Reconfiguration • Lower power usage time • Increased speed • Goal: area reduction with reduced reconfiguration time 7

Dynamic reconfiguration of FPGAs M 1 M 2 M 3 M 231 • 2 tool flows: • Modular Dynamic Reconfiguration (MDR) • Dynamic Circuit Specialization (DCS) 8

Modular Dynamic Reconfiguration (MDR) Mode 1 Mode 2 SYNTHESIS MAP PLACE ROUTE Configuration 1 Configuration 2 9

MDR • Different modes are implemented independently • Complete area is rewritten Results in long reconfiguration times 10

Dynamic Circuit specialization • Design with parameters: input signals that only change once a while • Implement dependency on parameters using dynamic reconfiguration 11

Dynamic circuit specialization Param. HDL • Input: annotated textual description of functionality SYNTHESIS TMAP Tunable circuit TPLACE TROUTE Param. Conf. 12

Parameterised HDL design in 0 in 1 in 2 in 3 sel 0 sel 1 out entity multiplexer is port( --BEGIN PARAM sel : in std_logic_vector(1 downto 0); --END PARAM in : in std_logic_vector(3 downto 0); out : out std_logic ); end multiplexer; architecture behavior of multiplexer is begin out <= in(conv_integer(sel)); end behavior; 13

Dynamic circuit specialization Param. HDL SYNTHESIS • Input: Annotated textual description of functionality • Internal representation: Tunable Circuit TMAP Tunable circuit TPLACE TROUTE Param. Conf. 14

Tunable circuit Tunable look-up table Tunable connection 15

Dynamic circuit specialization Param. HDL SYNTHESIS • Input: Annotated textual description of functionality • Internal representation: Tunable Circuit • Output: Parameterised configuration TMAP Tunable Circuit TPLACE TROUTE Param. Conf. 1 A 0101 0111 B 0 0 C 1111 A = sel 0 AND sel 1 B = sel 1 C = sel 0 OR sel 1 16

Dynamic Circuit Specialization • Reduced reconfiguration time • Takes as input 1 parameterised design • How to implement several modes with DCS? 17

Goal of our research • Develop tool flow for dynamic reconfiguration of multi-mode circuits • Reduce reconfiguration time • Combined implementation of different modes: Utilize similarities Increase correlation between configurations of the different modes 18

Novel tool flow Mode 1 Mode 2 SYNTHESIS MAP PLACE ROUTE Merge Configuration 1 Configuration 2 TROUTE Param. Conf. 19

Generating a Tunable multi-mode circuit 20

Combined placement: virtual 3 D FPGA • Simultanous placement of different LUT circuits on FPGA • Extension of a simulated annaeling placer 21

Different cost functions • CFRT: estimation of reconfiguration time (= number of switches that need to be rewritten in the routing) • CFWL: estimation of total wire length Tunable circuit 22

Reconfiguration time optimization • Uses “edge matching” - previously proposed * • Try to overlap connections of different modes • Connections that overlap don’t require parameterised bits in the routing *M. Rullmann and R. Merker, “Maximum edge matching for reconfigurable computing, ” Parallel and Distributed Processing Symposium, International, vol. 0, p. 179, 2006. 23

Wire-length optimization • Cost function that estimates total wire length needed by TRoute to implement Tunable circuit 24

Experiments • Implemented novel tool flow in our JAVA version of VPR • Regular expression matching hardware, constant coefficient FIR filters, and general MCNC benchmarks • Circuits of 200 -400 LBs • Only 2 modes considered • Comparison of MDR and DCS (this work) • Metrics: • Reconfiguration time • Wire length (of each mode separately) 25

Wire length 26

Results 27

Results 28

Conclusions • Using combined placement and DCS: • Around 5 X speedup of reconfig. time • Limited increase in wire length • Better to optimize for wire length during combined placement: this also reduces reconfiguration time! 27

Future work • Combining logic circuits instead of LUT circuits • Take configuration frames into consideration 28

An automatic tool flow for the combined implementation of multi-mode circuits Questions?