AMICSA 2008 31 August 02 September Sintra Portugal
AMICSA 2008 31 August – 02 September Sintra, Portugal Multi-Gbit/s Capable 65 nm CMOS Ser/Des Design Analysis for Space Application Dugoujon, L. 1; Hili, L. 2; Skoulaxinos, S. 3; Papadas, C. 3; Baguena, L. 4; Childerhouse, M. 5; Tonietto, D. 1; Ramet, S. 1; Badets, F. 1; Lavastre, S. 1; Briand, P. 1 1 STMicroelectronics (France); 2 ESA (The Netherlands); 3 ISD Athens (Greece); 4 Thales Alenia Space (France); 5 EADS Astrium (United Kingdom)
ST Global Presentation AMICSA 2008, September 02 STMicroelectroics, ISD EADS-Astrium Thales-Alénia Space 1
ST Global Presentation AMICSA 2008, September 02 STMicroelectroics, ISD EADS-Astrium Thales-Alénia Space 2
ST Global Presentation AMICSA 2008, September 02 STMicroelectroics, ISD EADS-Astrium Thales-Alénia Space 3
ST Global Presentation AMICSA 2008, September 02 STMicroelectroics, ISD EADS-Astrium Thales-Alénia Space 4
ST Space & High. Rel History & Policy First space supplier ever SCC-B Qualified (1979) Major ESA QPL contributor 1999: Creation of Rad Hard Design Center in ST-Sicily Expanding product portfolio ST Space & Hi. Rel Policy: Wide & stable Product Range offerings 300 krad at High Dose Rate & ELDRS (world leadership). Top level Heavy Ions requirements Top Level Space Quality Develops world business through QML-V Qual (1998) Full support & commitment to Europe national Space Programs: « Galileo. Sat » , « NGP » , « Digital Divide » , « COSMO » , « XMM » Dedication to custom products support AMICSA 2008, September 02 STMicroelectroics, ISD EADS-Astrium Thales-Alénia Space 5
Space Product Portfolio extract Available: Classical bipolar Transistor 2 N 2222’s series 300 krad ELDRS-free Bipolar Linear Regulators: RHFL 4913, L 7913 300 krad ELDRS-free Bipolar Op-Amps: RHF 43 B 300 krad Bipolar fast Op-Amps RHF 300=>RHF 350 series 100 krad Logic series: 54 HC 00’, CD 4000 B’s (Escc) 300 krad Logic serie: 54 AC 00’s (Qml-V) 300 krad 16 -bit Bus Interfaces: 54 VCXH 162244’s (Qml-V) 300 krad 12 -bit AD-Converter: RHF 1201 (Qml-V) 300 k. Rad 14 -bit ADC RHF 1401 Qml-V in 2008. In the pipe: Smd Diodes 100 k. Rad Power. MOS 100 k. Rad ELDRS-free 2 N Transistors redesign 1 N 5822 -5819 -5811 -5806 ‘s Clock Distributor RHFLVDS 111, 300 krad 32 -bit Bus Interface 54 VCXH 322245 EM avail, qual ‘ 08 300 krad ELDRS-free Quad Op-Amp RHF 484 300 krad ELDRS-free fast Op-Amp RHFS 111 of a new RH-SOI techn AMICSA 2008, September 02 STMicroelectroics, ISD EADS-Astrium Thales-Alénia Space 650 MHz, EM avail 6
ST INSIDE MSL ROVER Juno Spacecraft L = ~9’ JWST Telescope AMICSA 2008, September 02 STMicroelectroics, ISD EADS-Astrium Thales-Alénia Space 7
Need & constraints for Gbit/s Ser. Des Main application: Next Generation Telecom Satellites Digital Payload Partnering with European space industry primes: EADS-Astrium, Thales-Alenia Space Key objectives of KIPSAT project (under ESA contract): Assessment of ST 65 nm long term reliability Demonstration of Ser. Des 6. 25 Gbit/s performances Baseline for a space-grade ASIC technology AMICSA 2008, September 02 STMicroelectroics, ISD EADS-Astrium Thales-Alénia Space 8
System Architecture example AMICSA 2008, September 02 STMicroelectroics, ISD EADS-Astrium Thales-Alénia Space 9
Payload ASICs constraints Payload Processor ASIC requirements: 10 -30 Millions gates- 3 -8 Mb RAM - 6 Gbit/s Serial I/Os – 200 -400 MHz Processing Clock – Low dissipation – High-Reliability - Rad. Hard – Hermetic Package – Moderate customization costs for Manufacturers Such performances are only achievable with Deep Sub Micron ST proposed its CMOS 65 nm, commercially qualified in 2007. AMICSA 2008, September 02 STMicroelectroics, ISD EADS-Astrium Thales-Alénia Space 10
ESA Requirements / Intrinsic 65 nm 10 -30 Mgates 400 MHz clock Low power < 10 W >20 x 6. 25 Gbit/s HSSL Available before 2011 Non ITAR TID > 200 krad(Si) No SEL 80 Me. Vcm 2/mg 750 kgates/mm 2 2 GHz stdcells 5. 7 n. W/(MHz x gates) 1. 25 -7. 5 GBit/s modules Production in 2008 Made in Crolles (Isère-F) No variation 100 krad(Si) OK with process option SEE<10 -10/b/day in geo 15 years opl. lifetime Viable business model Efforts needed for SEUs Achievable MPW/MLR or Platform AMICSA 2008, September 02 STMicroelectroics, ISD EADS-Astrium Thales-Alénia Space 11
What? 65 nm for Space! Do we risk in such recent technology? What about: Rad-hard capabilities Reliability Cost Design flow AMICSA 2008, September 02 STMicroelectroics, ISD EADS-Astrium Thales-Alénia Space 12
Rad-hard maximisation Rad-hard capabilities measured under ESTEC-ST contracts (ST 130 nm, 90 nm, 65 nm and 45 nm) Usage of process option for SEL (1 mask) Experimental confirmation on worst case supply and Temp Validation of « analog » HSLL IP (LC-tank VCO) Re-use of SEU mitigation techniques (ST patented) on Std. Cells and clock-trees specificaly developed for this 65 nm platform Usage of a mix of SRAM or r. SRAM (ST patent) cuts to be defined with end-users RH by design ST (+CERN) know-how enriched by end -users cooperation. AMICSA 2008, September 02 STMicroelectroics, ISD EADS-Astrium Thales-Alénia Space 13
Reliability maximisation Analysis of reliability figures from Std qualification Systematic application of ST Di. R methodology (focusing HCI and NBTI) with dedicated tools for ageing simulations Eventual specific layout rules for reliability enhancement Study of tighter controls at process level AMICSA 2008, September 02 STMicroelectroics, ISD EADS-Astrium Thales-Alénia Space 14
Reliability summary for ST 65 nm LEVEL 1 (Wafer Level Reliability): Even with Worst Case test conditions, all but two items (NBTI+HCI) exceed 15 years spec on test structures. NBTI + HCI: Accurate simulation methodology + design guidelines provide means to exceed 15 years on actual IC. LEVEL 2 (Early Failure Rate + Over Life Test ) : Qualification step: 8 fails out of ~ 6000 samples. All explained by defectivity/SPC. Post-Qual monitoring: 0 fail (10 years) out of ~4000 samples. Huge enhancement of D 0 with the PDF program. AMICSA 2008, September 02 STMicroelectroics, ISD EADS-Astrium Thales-Alénia Space 15
Device Reliability Modeling VG+ Goal: Cover all VG/VD domain HCI PBTI VG Off-state VD+ OS NM DR AI N SO UR CE GRILLE GATE SUBSTRAT BULK VD VG+ PM OS Off-state VD+ NBTI HCI AMICSA 2008, September 02 STMicroelectroics, ISD EADS-Astrium Thales-Alénia Space 16
Transistor-Level Reliability Simulation Flow Reliability model (Eldo UDRM) • Extended models Reliability parameters SPICE model Description of Transistor Stress as function of Activity Description of SPICE parameters evolution as function of Stress Netlist • Age. lib object Library Aged Results Simulate Aged Simulate Fresh Comparison Model Parameters (Fresh) Aging related commands Updated SPICE parameters Nominal Results Stress analysis Eldo Stress File AMICSA 2008, September 02 Optional STMicroelectroics, ISD EADS-Astrium Thales-Alénia Space 17
Reliability Modeling/Simulation Flow NBTI, HCI stress experiments Multiple Vgs/Vds conditions Model describing the degradation f(Ids, Ib, W)-HCI Extractionof f(Vgs, Vds, T, L, t)-NBTI degradation parameters such as Vt, gm and. IV curves during stress Model. SPICE parameter evolution Reliability Modeling Add to. Spice model of degradation of At designer end STEP 1 Estimation Different transistors Evaluation of degraded. SPICE Iterativ e Circuit spice n/l + Input stimuli Reliability Simulation Running Simulation AMICSA 2 2008, September 02 STEP STMicroelectroics, ISD EADS-Astrium Thales-Alénia Space with degraded models Compare 18
Silicon Validation Inverter ring in 65 nm technology Simulations similar to HTOL of fab silicon AMICSA 2008, September 02 STMicroelectroics, ISD EADS-Astrium Thales-Alénia Space 19
NBTI simulation: digital buffer Note the delay introduced by the NBTI in comprison to the same buffer without NBTI AMICSA 2008, September 02 STMicroelectroics, ISD EADS-Astrium Thales-Alénia Space 20
NBTI: Vth shift Illustration of the input threshold shift in I/O buffer AMICSA 2008, September 02 STMicroelectroics, ISD EADS-Astrium Thales-Alénia Space 21
SERDES principle /2 Data Slice Clock Slice Data Slice I Q 3. 125 GHz 4 to 10 data Slices per Clock Slice Ref Clk RX input offset Cancellation TX output AMICSA 2008, September 02 STMicroelectroics, ISD EADS-Astrium Thales-Alénia Space 22
Ser. Des features Technology 65 nm LP , 7 metal , triple VT, Dual Gate oxide 50 A Power S. Single 1 V 2 Data Rates 1. 25, 2. 5, 3. 125, 3. 75, 5, 6. 25, 7. 5 Gbps with a single 156. 25 ref. clock. (125 Mhz ref clock supported ) IO RX equal. adaptive , linear up to 15 d. B + 4 tap DFE TX: 5 Tap FIR, programmable Stackability 4 links per macro Power (m. W/Link) 250 max @7. 5 Gbps, 200 max @ 5 Gbps Area/Bump 900 u x 640 u /link ( 10 bumps) designed for 2 -2 -2 FCBGA Reference CEI-6 LR Use: Long reach backplanes lines Maturity IP Test chip fully tested, ASIC products in qualification Doc Data sheet available ; CAD views available AMICSA 2008, September 02 STMicroelectroics, ISD EADS-Astrium Thales-Alénia Space 23
Ser. Des Packaging constraints q. Bump q usage q. Power consumption table Clock + 4 Data slices Bump out Edge of die data slice clock slice power supply 1. 2 1. 3 5. 00 172 200 6. 25 187 7. 5 201 Rate 1. 1 1. 25 2. 50 3. 125 3. 75 Core side Update : 1 clock slice support 8 data slices (tbv) 12 @7. 5 G (tbv) 16 @6. 25 q. Bump 63 68 250 73 q. Power at Vod peak =400 m. V to ball ratio q. Package notes Bump Ball Signal 1 1 q. Require 1 Resistor and 1 Cap on package AVDD 4 1 q. Designed for FCBGA build up 2 -2 -2 substrate. AGND 4 1 VCC TBD 1 AMICSA 2008, September 02 STMicroelectroics, ISD EADS-Astrium Thales-Alénia Space 24 1. 3
Ser. Des Terrestrial > Space Organic fc. BGA Pkg, 17 x 17, 2 -2 -2, 256 Balls, 1. 0 mm ball pitch Hermetic package solution under analysis Target BER <10 -18 (on CAT 4 K legacy backplane) ESA specs of <10 -12 (medias to be defined) 250 m. W max power @7. 5 Gbps, 200 m. W max power @ 5 Gbps ESA spec=200 m. W, slight power reduction under study Re-simulations with ageing effects and eventual rework 15 -20 years verification in worst case conditions AMICSA 2008, September 02 STMicroelectroics, ISD EADS-Astrium Thales-Alénia Space 25
SEUs mitigation techniques Analysis of Ser. Des critical areas Replacement of standard dffs by robust dffs (ST patents) Use of robust clock-trees (ST patents) where critical Implementation of TMV where necessary Continuous reading of configuration registers and automatic recovery in case of corruption AMICSA 2008, September 02 STMicroelectroics, ISD EADS-Astrium Thales-Alénia Space 26
Ser/Des Validation (1) Astrium has evaluated and tested Texas and Xilinx Ser/Des systems. Texas TLK 2711 – 1. 6 to 2. 5 Gbps Tested with parallel clock at 1. 6 Gbps and 2. 5 Gbps. Tested with nominal supply voltage (2. 5 V) +/-0. 1 V. No noticeable correlation was apparent. Tested with various lengths of differential stripline traces and 50 ohm matched length coax cable. Stripline lengths of 10, 15, 20, 30, 40 inches and combinations thereof. Tested using built in PRBS (27 -1) in a loop back configuration. Eye measurements Jitter measurements BER measurements Error free, from 1. 6 Gbps to 2. 5 Gbps, within a determined distance. AMICSA 2008, September 02 STMicroelectroics, ISD EADS-Astrium Thales-Alénia Space 27
Ser/Des Validation (2) Xilinx ML 321 – 3. 125 Gbps Tested at 3. 125 Gbps and 2. 5 Gbps using on-board and external oscillator. Tested with various lengths of differential stripline traces and 50 ohm matched length coax cable. Stripline lengths of 10, 15, 20, 30, 40 inches and combinations thereof. Tested using built in PRBS generator using various polynomials in a loop back configuration with 33% pre-emphasis. Eye and jitter measurements. BER measurements. . Error free, at 2. 5 & 3. 125 Gbps, within a determined distance, with short PRBS polynomials. Xilinx MK 322 – 10 Gbps Tested at 5 Gbps and 10 Gbps with various lengths of differential stripline traces and 50 ohm matched length coax cable. Tested using built in PRBS generator using various polynomials in a loop back configuration with default and optimised pre-emphasis. Eye and jitter measurements. BER measurements. Virtually error free, at 10 Gbps, over shorter distances. AMICSA 2008, September 02 STMicroelectroics, ISD EADS-Astrium Thales-Alénia Space 28
Ser/Des Validation (3) “Quatuor” Validation Test Quatuor configurations that are likely to be used in telecoms payloads. Test various parametric configurations, e. g. pre-emphasis, output level, equalization. Consider requirements for autonomous link establishment and maintenance in space environment subject to SEE. Prove that unidirectional links can be established, that link performance degradations and link loss maybe detected and that links can be re-established. Test with various media as expected to be used in telecoms payloads. Test impact of clock quality on measured BER. Perform eye and jitter measurements. Estimate best achievable BER (assuming ideal Rx and clock recovery) in the absence of other noise sources. Measure BER. Participate in radiation testing of Quatuor Advise on the design of evaluation board ensuring direct access to parallel digital data. Consider the design of dedicated test hardware, for BER, for link establishment and maintenance, for SEE testing. Consider hiring dedicated parallel BER Tester. AMICSA 2008, September 02 STMicroelectroics, ISD EADS-Astrium Thales-Alénia Space 29
Validation with TAS (1/1) Thales Alenia Space has been implementing such kind of components for a long time, starting with first generation of 400 Mbits/s links, that are now in orbit More recent payloads required far higher speeds and Serdes components from 1 Gbits/s to over 3 Gbits/s have been evaluated in our labs We are presently working on last generation of components up to 10 Gbits/s 2 methodologies are being used: Elaboration of our own test/evaluation breadboard including proprietary BER measurement environment on specific breadboard Utilization of commercial tools for BER on breadboard: BER tester Anritsu 1632 A up to 3, 2 Gbps BER tester Agilent N 4901 A up to 12 Gbps Thales Alenia Space expertise and means will support the present HSSL development AMICSA 2008, September 02 STMicroelectroics, ISD EADS-Astrium Thales-Alénia Space 30
Cost mitigation Hi-rel Rad-Hard stdcells & IPs selection Metal-Customizable Logic Low troughput/power consumption FPGA AMICSA 2008, September 02 Structured ASIC STMicroelectroics, ISD EADS-Astrium Thales-Alénia Space Full cust. ASIC 31
Conclusions CMOS 65 nm provides needed performances for next generation satellite telecom payload processors NBTI and HCI are well modeled and simulated TID is not an issue, mitigation of SEUs needed High performances Ser. Des derived from a proven IP used in telecom networking products Robust dff + clock trees available libraries End-users participate to demonstrator chip (4 x 6. 25 Gbit/s) definition, trade-offs, CDRs and tests 2 sd phase will target to provide ASIC capability AMICSA 2008, September 02 STMicroelectroics, ISD EADS-Astrium Thales-Alénia Space 32
Thank you! See ST Rad-hard products at www. st. aerospace. com AMICSA 2008, September 02 STMicroelectroics, ISD EADS-Astrium Thales-Alénia Space 33
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