Algorithms for VLSI Design Automation Instructor D Zhou

Algorithms for VLSI Design Automation Instructor D. Zhou zhoud@utdallas. edu Phone: 972 883 4392 Office: ECN 4. 610 Dragon Star Shot Course

Outline History and the road map Traditional design flow Physical design fundamentals Performance issues System on chip 12/18/2021 Dragon Star Shot Course 2

History and the road map The history of IC n n n The invention of transistor The invention of integrated circuit IC has changed our life Moore’s Law n IC performance and complexity have been doubled in every two years Road Map 12/18/2021 Dragon Star Shot Course 3

The invention of transistor John Bardeen, Walter Brattain & Wiliam Shockley in vented “The first transistor” in 1947. 12/18/2021 Dragon Star Shot Course 4

The invention of integrated circuit Jack Kilby & Robert Noyce inveted “The Integrated Circuit” in 1958. 12/18/2021 Dragon Star Shot Course 5

Moore’s Law q In 1965, Gordon Moore predicted that the number of transistors that can be integrated on a die would double every 18 to 14 months (i. e. , grow exponentially with time). q Amazingly visionary – million transistor/chip barrier was crossed in the 1980’s. l 2300 transistors, 1 MHz clock (Intel 4004) - 1971 l 16 Million transistors (Ultra Sparc III) l 42 Million, 2 GHz clock (Intel P 4) - 2001 140 Million transistor (HP PA-8500) l CSE 477 L 01 Introduction. 6 Irwin&Vijay, PSU, 2002

Intel 4004 Microprocessor CSE 477 L 01 Introduction. 7 Irwin&Vijay, PSU, 2002

Intel Pentium (IV) Microprocessor CSE 477 L 01 Introduction. 8 Irwin&Vijay, PSU, 2002

Moore’s Law in Microprocessors Transistors on lead microprocessors double every 2 years 1000 2 X growth in 1. 96 years! Transistors (MT) 100 10 486 1 386 286 0. 1 0. 01 8086 8080 8008 4004 8085 0. 001 1970 CSE 477 L 01 Introduction. 9 P 6 Pentium® proc 1980 1990 Year Courtesy, Intel 2000 2010 Irwin&Vijay, PSU, 2002

Evolution in DRAM Chip Capacity human memory human DNA 4 X growth every 3 years! 0. 07 m 0. 13 m 0. 18 -0. 25 m book 0. 35 -0. 4 m 0. 5 -0. 6 m 0. 7 -0. 8 m 1. 0 -1. 2 m encyclopedia 2 hrs CD audio 30 sec HDTV 1. 6 -2. 4 m page CSE 477 L 01 Introduction. 10 Irwin&Vijay, PSU, 2002

Die Size Growth Die size grows by 14% to satisfy Moore’s Law Die size (mm) 100 10 8080 8008 4004 8086 8085 286 386 P 6 486 Pentium ® proc ~7% growth per year ~2 X growth in 10 years 1 1970 CSE 477 L 01 Introduction. 11 1980 1990 Year Courtesy, Intel 2000 2010 Irwin&Vijay, PSU, 2002

Clock Frequency Lead microprocessors frequency doubles every 2 years 10000 2 X every 2 years Frequency (Mhz) 1000 P 6 100 486 10 8085 1 0. 1 1970 CSE 477 L 01 Introduction. 12 8086 286 Pentium ® proc 386 8080 8008 4004 1980 1990 Year Courtesy, Intel 2000 2010 Irwin&Vijay, PSU, 2002

Power Dissipation Lead Microprocessors power continues to increase Power (Watts) 100 P 6 Pentium ® proc 10 8086 286 1 8008 4004 486 386 8085 8080 0. 1 1974 1978 1985 1992 2000 Year Power delivery and dissipation will be prohibitive CSE 477 L 01 Introduction. 13 Courtesy, Intel Irwin&Vijay, PSU, 2002

Power Density (W/cm 2) 10000 Rocket Nozzle 1000 Nuclear Reactor 100 8086 10 4004 Hot Plate P 6 8008 8085 Pentium® proc 386 286 486 8080 1 1970 1980 1990 Year 2000 2010 Power density too high to keep junctions at low temp CSE 477 L 01 Introduction. 14 Courtesy, Intel Irwin&Vijay, PSU, 2002

Technology Trend International Technology Roadmap for Semiconductors (ITRS) Production year MPU Gate length (nm) 2002 2003 2004 2005 2006 2007 75 65 53 45 40 35 Clock (GHz) 2. 3 3. 1 4. 0 5. 2 5. 6 6. 7 Metal layers 8 8 8 9 9 9 Supply voltage (V) 1. 0 0. 9 0. 7 Microelectronics Department, Fudan University

Traditional design flow (see slides designflow) What has not been addressed in depth n n n Understand application Architecture synthesis Verification is not complete 12/18/2021 Dragon Star Shot Course 16

12/18/2021 Dragon Star Shot Course 17

Microelectronics Department, Fudan University

Performance issues Speed Noise Clock distribution Power distribution Low power 12/18/2021 Dragon Star Shot Course 19

SOC A low cost solution Challenges n n n Modeling Simulation Mixed signal Different processing Timing 12/18/2021 Dragon Star Shot Course 20

Agenda Dealing with technology n n n Masks Front-end manufacturing Back-end manufacturing Application requirements Putting it all together 12/18/2021 Dragon Star Shot Course 21

Agenda Dealing with technology n n n Masks Front-end manufacturing Back-end manufacturing Application requirements Putting it all together 12/18/2021 Dragon Star Shot Course 22

Semiconductor Process Flow EDA Systems $1050 B $3. 6 B Design EDA • Computers $2. 7 B • Communications Comp • Consumer Platforms • Industrial, Military… Embedded SW $0. 8 B IP $0. 9 B Semiconductors • Micros, DSP • Memory • ASIC, ASSP $119 B $45 B Wafer $4 B $25 B • Analog, Discrete $25 B Masks $2. 8 B Mask Data • Manufacturing $2. 3 B Masks • Tools $0. 5 B Manufacturing $24 Front-End • Process Auto $1 B • Lithography $6 B • Etch/Doping $6 B • Diffusion $1 B • Deposition $5 B • Other (CMP, Ion, Photoresist, etc. ) $5 B Back-End Manufacturing $6 Chips • Bonding • Packaging • Test equipment Weisel. Star Dataquest, ICI, Synopsys Estimates 12/18/2021 Market size for 2001 Sources: Thomas Dragon Shot Course $1 B $2 B $3 B 23

Exploding Mask Costs Year Node Cost Data 1999 2002. 18µm. 13µm $200 -400 K $500 K-1 M 16 GB 64 GB 2004. 9µm $800 K 1. 2 M 256 GB 2007. 065µm $1 -2 M 1024 GB Raster scan patterning exposure time for a 110 mm x 110 mm mask is 6. 5 hrs and 20 hrs with fine granularities (60 nm vs. 120 nm pixel size) Largest contribution to mask making is mask exposure time (capital cost ~$20 M) RET is being absorbed by CAD vendors into layout verification / tape-out suites. RET may move up Dragon into Star routing, placement Shot Course Source: 12/18/2021 Thomas Weisel Partners 24

Front-End Processing EDA Systems $1050 B $3. 6 B Design EDA • Computers $2. 7 B • Communications Comp • Consumer Platforms • Industrial, Military… Embedded SW $0. 8 B IP $0. 9 B Semiconductors • Micros, DSP • Memory • ASIC, ASSP $119 B $45 B Wafer $4 B $25 B • Analog, Discrete $25 B Masks $2. 8 B Mask Data • Manufacturing $2. 3 B Masks • Tools $0. 5 B Manufacturing $24 Front-End • Process Auto • Lithography • Etch/Doping • Diffusion • Deposition • Other (CMP, Ion, Photoresist, etc. ) $1 B $6 B $1 B $5 B Back-End Manufacturing $6 Chips • Bonding • Packaging • Test equipment $1 B $2 B $3 B Market size for 2001 Sources: Thomas Weisel Dataquest, ICI, Synopsys Estimates 12/18/2021 Dragon Star Shot Course 25

Interconnect Exploding number of metal layers, mask cost Large number of vias diminishes yield Increasingly complex process rules • Include pattern density & shape management in Via Stack layout, extraction Multiple • Limit vias / multiple vias Array n Metal Min, max, spacing, width n Antenna n Signal EM Number of vias for a given load, 12/18/2021 Dragon Star Shot Course 26 frequency n

CD Variation Across a Wafer Line. Width [nm] Wafer Map for No-DPC Horizontal Isolated Structures 2. 3 2. 2 2. 1 2. 0 1. 9 1. 8 150 x 10 -7 100 Wafer Y 50 0 0 20 40 60 Wafer Y Incorporate analysis of timing variation into extraction & static timing analysis Source: 12/18/2021 Spanos, UCB Dragon Star Shot Course 27

Physical design for Yield / Reliability Aggressive via minimization in routing Insert redundant vias Space / Width Limit Current Density 12/18/2021 Dragon Star Shot Course 28

Back-End: Assembly and Packaging EDA Masks Systems $1050 B • Computers • Communications • Consumer • Industrial, Military… Embedded SW $0. 8 B IP $0. 9 B Semiconductors • Micros, DSP • Memory • ASIC, ASSP $3. 6 B Design EDA $2. 7 B Comp Platforms $119 B $45 B Wafer $4 B $25 B • Analog, Discrete $25 B $2. 8 B Mask Data • Manufacturing $2. 3 B Masks • Tools $0. 5 B Manufacturing $24 Front-End • Process Auto $1 B • Lithography $6 B • Etch/Doping $6 B • Diffusion $1 B • Deposition $5 B • Other (CMP, Ion, Photoresist, etc. ) $5 B Back-End Manufacturing $6 Chips • Bonding • Packaging • Test equipment $1 B $2 B $3 B Market size for 2001 Sources: Thomas Weisel Dataquest, ICI, Synopsys Estimates 12/18/2021 Dragon Star Shot Course 29

Assembly and Packaging The chip is assembled into a package that provides the contact leads for the chip. A wire-bonding machine attaches wires to the leads of the package; or this is achieved using flip chip die attach. Modern packages can be very complex The package is the bridge between silicon and system Differentiator: Performance, form factor, fit, thermal conduction, reliability, and cost 12/18/2021 Dragon Star Shot Course 30

IC / Package Co-Design for Flip Chip Lid Chip Package Pwr, Gnd Signal Solder balls Board 12/18/2021 • Design • Analyis • Package feasibility • Extraction RLC • Simulation Spice • Bump patterning, assignment • P/G assignment • Driver placement • Routing Dragon Star Shot Course 31

So. C Packaging Trends by 2005 n n n Cost: 0. 29¢ to 2. 28¢ / pin Pins / package: 120 – 3000 Performance: 600 MHz – 2 GHz Integrating complete (sub)systems on a chip is often driven by packaging n n Less I/O, power, area, & cost Higher on-chip speed, reliability Complex packages and Multi-chip modules that require routing and analysis, driven by mixed-signal, RF, memory integration 12/18/2021 Dragon Star Shot Course 32

Back-End: Testing and Automatic Test Equipment EDA Systems $1050 B $3. 6 B Design EDA • Computers $2. 7 B • Communications Comp • Consumer Platforms • Industrial, Military… Embedded SW $0. 8 B IP $0. 9 B Semiconductors • Micros, DSP • Memory • ASIC, ASSP $119 B $45 B Wafer $4 B $25 B • Analog, Discrete $25 B Masks $2. 8 B Mask Data • Manufacturing $2. 3 B Masks • Tools $0. 5 B Manufacturing $24 Front-End • Process Auto $1 B • Lithography $6 B • Etch/Doping $6 B • Diffusion $1 B • Deposition $5 B • Other (CMP, Ion, Photoresist, etc. ) $5 B Back-End Manufacturing $6 Chips • Bonding • Packaging • Test equipment $1 B $2 B $3 B Market size for 2001 Sources: Thomas Weisel Dataquest, ICI, Synopsys Estimates 12/18/2021 Dragon Star Shot Course 33

Key Trends By 2005 n Cost: $2 -5 k/pin ( high performance) n Pins / package: 1900 n Performance: up to 2 GHZ Tester timing accuracy growing at 12% per year ASIC speeds growing at 30% per year IDDQ becoming less meaningful n n For every 80 m. V of VT decrease Ioff increases 10 x!! Higher leakage currents make IDDQ values increase dramatically as transistor density increases More mixed-signal testing Dragon Star Shot Course 12/18/2021 34

Agenda Dealing with technology n n n Masks Front-end manufacturing Back-end manufacturing Application requirements Putting it all together 12/18/2021 Dragon Star Shot Course 35

Application Requirements EDA Systems $1050 B $3. 6 B Design EDA • Computers $2. 7 B • Communications Comp • Consumer Platforms • Industrial, Military… Embedded SW $0. 8 B IP $0. 9 B Semiconductors • Micros, DSP • Memory • ASIC, ASSP $119 B $45 B Wafer $4 B $25 B • Analog, Discrete $25 B Masks $2. 8 B Mask Data • Manufacturing $2. 3 B Masks • Tools $0. 5 B Manufacturing $24 Front-End • Process Auto $1 B • Lithography $6 B • Etch/Doping $6 B • Diffusion $1 B • Deposition $5 B • Other (CMP, Ion, Photoresist, etc. ) $5 B Back-End Manufacturing $6 Chips • Bonding • Packaging • Test equipment $1 B $2 B $3 B Market size for 2001 Sources: Thomas Weisel Dataquest, ICI, Synopsys Estimates 12/18/2021 Dragon Star Shot Course 36

Heterogeneity - So. C Digital n n Control µP DSP Interfaces Memory n n n 12/18/2021 Dragon Star Shot Course Analog RF Power MEMs IP SRAM DRAM FLASH 37

What EDA Must Provide… 12/18/2021 System level design Soc design&test, verification methodology Need hierarchy in the design flow Analog, digital, RF, MEMs IP for soc construction / verification: processors, memory, peripherals, etc. Soc design for debug (debug busses and 38 Dragon Star Shot Course

ASIC, ASSP, ASIP, GA, FPGA ASIC & ASSP differ only by how they are sold and used, not by how they are designed Early market characteristics ASICs Late market characteristics ASSPs Trend toward application-specific instruction processors n Many processors on a chip Metal Programmability (GA) gaining attention again SW Programmable (FPGA), reconfigurable parts gaining importance Embedded FPGA / GA 12/18/2021 Dragon Star Shot Course 39

Power 1400 Dynamic power density 1200 m. W/mm 2 1000 800 600 Leakage power density 400 200 0 0. 18 µm 12/18/2021 0. 13 µm Dragon Star Shot Course 0. 10 µm 0. 05 µm 40

Solutions for Low Power Design Power modeling and analysis Clock gating and clock tree optimization Variable Vdd n n n Power gating Multi - Vdd Dynamic voltage scaling Leakage optimization using multi-Vt Modelling process variation Support Asynchronous design 12/18/2021 Dragon Star Shot Course 41

130 nm Leakage power [0. 0 -1. 0] n. W Leakage power [0. 0 -240. 0] n. W 180 nm Dual Vt Cell number [0 -467] 12/18/2021 Dragon Star Shot Course Cell number [0 -519] 42 From Ali Dasdan

Speed Determined by interconnect The primary physical effect of concern is cross-coupled capacitance plus the Miller effect. This may cause: n n functional errors in analog circuitry or dynamic logic timing errors in static digital circuitry V dd R DV = IR V -DV dd I R V ss IR Drop (static leakage and dynamic IR drop) handled in power Other important effects & features are Inductance, CD variation, EM 12/18/2021 Dragon Star Shot Course 43

Agenda Dealing with technology n n n Masks Front-end manufacturing Back-end manufacturing Application requirements Putting it all together 12/18/2021 Dragon Star Shot Course 44

Putting it All Together: EDA Systems $1050 B $3. 6 B Design EDA • Computers $2. 7 B • Communications Comp • Consumer Platforms • Industrial, Military… Embedded SW $0. 8 B IP $0. 9 B Semiconductors • Micros, DSP • Memory • ASIC, ASSP $119 B $45 B Wafer $4 B $25 B • Analog, Discrete $25 B Masks $2. 8 B Mask Data • Manufacturing $2. 3 B Masks • Tools $0. 5 B Manufacturing $24 Front-End • Process Auto $1 B • Lithography $6 B • Etch/Doping $6 B • Diffusion $1 B • Deposition $5 B • Other (CMP, Ion, Photoresist, etc. ) $5 B Back-End Manufacturing $6 Chips • Bonding • Packaging • Test equipment $1 B $2 B $3 B Market size for 2001 Sources: Thomas Weisel Dataquest, ICI, Synopsys Estimates 12/18/2021 Dragon Star Shot Course 45

So. C Design Verification IP Physical Implementation Design Database Design Planning Architecture Design Smart Verification Extraction Physical Verification Languages Assertions and Testbenches Power Test Synthesis IP Physical Timing and Signal Integrity Design Services Mixed Signal / Analog Mask Synthesis / OPC 12/18/2021 Dragon Star Shot Course 46

Implementation Nodes 12/18/2021 Dragon Star Shot Course 47

Implementation Nodes 12/18/2021 Dragon Star Shot Course 48

Verification IP Architecture Design Smart Verification Mixed Signal / Analog 12/18/2021 Languages Assertions and Testbenches Functional Verification Driven by complexity Verification models (IP) Avenues of development n n Higher levels Performance Integration New (formal) technologies Emulation competes with n n Prototyping (enabled by multi-million gate FPGAs) Compute farms (Linux) Dragon Star Shot Course 49

Verification IP Architecture Design Smart Verification Mixed Signal / Analog Languages Assertions and Testbenches Functional Verification 2003 Standard based IP, Star IP on AMBA (System) Verilog for HW System. C for system level design (SW) Languages for testbenches, assertions being standardized Integrated simulation n n Testbenches n n n Language Assertions (monitor) Constraint solver Formal verification n n 12/18/2021 (System)Verilog/VHDL Fast Spice/Spice Equivalence checking Semi-Formal property checking Dragon Star Shot Course 50

Summary Dealing with technology n Masks RET, OPC, PSM n Front-end manufacturing Interconnect, CD variation, dishing, DFM n Back-end manufacturing Packaging, test Application requirements n Heterogeneity, cost, power, speed Putting it all together n Implementation flow, verification flow 12/18/2021 Dragon Star Shot Course 51