AIDEMC Low emission Digital Circuit Design Department of
- Slides: 8
AID–EMC: Low emission Digital Circuit Design Department of Electrical Engineering (ESAT) Logic style 1. 2. 3. Standard CMOS logic Pseudo NMOS logic MCML (MOS Current Mode Logic--differential version of CSL) 4. CSL (CMOS Current Steering Logic) MICAS
Why CSL ? Department of Electrical Engineering (ESAT) Target : Mixed-Mode Automotive Electronics Design Key aspect : di/dt + Power + Area + Speed Current Steering Logic MICAS
CSL – Static Characteristic Department of Electrical Engineering (ESAT) MICAS Vdd=2. 5 v I=20 u. A Design Parameter: R=
CSL – Noise Margin Department of Electrical Engineering (ESAT) MICAS Vdd=2. 5 v I=20 u. A
CSL – Dynamic Characteristic Department of Electrical Engineering (ESAT) MICAS Vdd=2. 5 v I=20 u. A
The Effect of Decoupling Capacitance Department of Electrical Engineering (ESAT) MICAS 1 p Cd Vdd=3. 3 v I=10 u. A R=6 10 p, 100 p, 1 n, 10 n There is a Trade off !
Comparison of 16 -bit RCA Department of Electrical Engineering (ESAT) Power vs. Frequency (16 -bit RCA) MICAS Note: CMOS Vdd=1. 5 v CSL 9. 00 E-04 The curve of CSL 16 -bit RCA was obtained by calculating the real speed F of the circuit, given the different supply current I. 8. 00 E-04 Power(Watt) 7. 00 E-04 Solution: 6. 00 E-04 5. 00 E-04 power consumption management 4. 00 E-04 • power down strategies, • sleeping transistors, • … 3. 00 E-04 2. 00 E-04 1. 00 E-04 0. 00 E+00 0 50 100 150 Frequency(Mhz) 200 250 300
Spectrum Analysis of di/dt Department of Electrical Engineering (ESAT) MICAS Power Spectral Analysis of the CMOS 16 -bit RCA 150 140 30 db decrease 130 Power 120 110 100 90 80 705 10 GABARIT ? 6 10 7 10 8 10 Frequency (Hz) 9 10 10 10
