AHDL Danny Mok Altera HK FAE dmokaltera com

AHDL培训教材 Danny Mok Altera HK FAE (dmok@altera. com) Copyright © 1997 Altera Corporation

接上页 n 创建 AHDL文件 Copyright © 1997 Altera Corporation

接上页 n 把你的 ADHL保存为 name. TDF的形式 两者必 须相同 Copyright © 1997 Altera Corporation

接上页 点击这 个图标 Copyright © 1997 Altera Corporation

AHDL模板 忘了怎么办？ Copyright © 1997 Altera Corporation If-then-else case-end case loop-end loop ? ? …? ? ? 修改代码

一般的AHDL文件格式 SUBDESIGN decode 1 ( input_pin_name : INPUT; input_bus_name[15. . 0] : INPUT; output_pin_name : OUTPUT; output_bus_name : OUTPUT; ) BEGIN ouptut_pin_name = input_pin_name; output_bus_name = input_bus_name; END; 关键字 定义I/O端口 逻辑表达式 AHDL格式 Copyright © 1997 Altera Corporation

第一个 AHDL设计－地址译码器 SUBDESIGN decode 1 ( a[3. . 0] : input; chip_enable : output; ) begin chip_enable = (a[3. . 0] == H"7"); end; Chip_enable = a 0 & a 1 & a 2 & !a 3 Copyright © 1997 Altera Corporation

更多的优势 SUBDESIGN decode 1 ( a[3. . 0] : input; chip_enable : output; ) begin chip_enable = (a[3. . 0] == B"1 x 0 x"); end; 比较器的某些输 入比特可以忽略 Copyright © 1997 Altera Corporation

使用常数（Constant）功能 n 如果文件中相同的数字、字符串或者算术表达式重复出现多 次，使用常数（Constant）来表示它们 修改一处即可修 n 优点 改整个设计文件 – 如果修改，只需改变一个声明 CONSTANT IO_ADDRESS = H"A"; 在关键字 SUBDESIGN 之前，定义常数 （ CONSTANT） Copyright © 1997 Altera Corporation SUBDESIGN decode 1 ( a[3. . 0] : input; chip_enable : output; ) begin chip_enable = (a[3. . 0] == IO_ADDRESS); if (a[3. . 0] == IO_ADDRESS) then ……. . . end;

常数（ Constant）的其他用途 n 常数使用举例 Constant IO_ADDRESS = H” 370”; Constant FOO = 1+2*3 - LOG 2(256); Constant FOO_PLUS_one = FOO + 1; 定义一个常数值 定义一个算术表达式 通过预先定义的常数 定义新的常数 Copyright © 1997 Altera Corporation

组合逻辑的实现 图形设计文件 AHDL设计文件 SUBSDESIGN decode 1 ( a 0, a 1, b : input; out 1, out 2 : output; ) begin out 1 = a 0 & !a 1; out 2 = out 1 # b; end; out 1 = a 0 & !a 1 out 2 = a 0 & !a 1 # b Copyright © 1997 Altera Corporation

定义节点 图形方式 AHDL 方式 temp out 2 = a 0 & !a 1 # b out 3 = a 0 & !a 1 & d Copyright © 1997 Altera Corporation SUBDESIGN decode 1 ( a 0, a 1, b, d: input; out 2, out 3 : output; ) variable temp : node; begin temp = a 0 & !a 1; out 2 = temp # b; out 3 = temp & d; end;

总线操作 SUBDESIGN decode 1 ( a[3. . 0], b[3. . 0] : input; out[3. . 0] : output; ) begin out 0 = a 0 & b 0; out 1 = a 1 & b 1; out 2 = a 2 & b 2; out 3 = a 3 & b 3; end; Copyright © 1997 Altera Corporation SUBDESIGN decode 1 ( a[3. . 0], b[3. . 0] : input; out[3. . 0]: output; ) begin out 1[] = a[] & b[]; end; 功能相同 但容易描述

总线操作的其他方式 总线操作 a[9. . 0], b[9. . 0] – – – – – a[] = b[]; a[7. . 4] = b[9. . 6]; a[9. . 8] = VCC; a[9. . 8] = 1; a[9. . 8] = 2; a[9. . 8] = 3; a[3. . 0] = GND a[3. . 0] = 0; temp = b 0& b 1; a[2. . 1] = temp Copyright © 1997 Altera Corporation a 7=b 9, a 6=b 8, a 5=b 7, a 4=b 6 a[9. . 8] connect to VCC a[9. . 8] = B” 01” a[9. . 8] = B” 10” a[9. . 8] = B” 11” a[3. . 0] connect to GND a[3. . 0] = B” 0000” a 2 = temp, a 1 = temp

高级总线操作 n 总线 – b[3. . 0] • b 3, b 2, b 1, b 0 (having 4 members) • MSB is b 3, LSB is b 0 n 总线阵列 – a[3. . 0][2. . 0] • a 3_2, a 3_1, a 3_0, a 2_2, a 2_1, a 2_0, a 1_2, a 1_1, a 1_0, a 0_2, a 0_1, a 0_0 (having 12 members) • MSB is a 3_2, LSB is a 0_0 a[3. . 2][1. . 0] = b[]; a 3_1 = b 3 a 2_1 = b 1 Copyright © 1997 Altera Corporation a 3_0 = b 2 a 2_0 = b 0 首先对低位比特赋值

真值表 i[3. . 0] 0 1 2 F Segment 7 0 1 2 F a f e b g d Copyright © 1997 Altera Corporation c 修改非常方便

IF-THEN-ELSE语句 SUBDESIGN priority ( low, medium, high : input; highest_level[3. . 0] : output; ) begin if ( high == B” 1”) then highest_level[] = B” 1000”; elsif (medium == B” 1”) then highest_level[] = B” 0100”; elsif (low == B” 1”) then highest_level[] = B” 0010”; else highest_level[] = B” 0001”; end if; end; Copyright © 1997 Altera Corporation

需要4个 逻辑单元 Copyright © 1997 Altera Corporation

CASE语句 SUBDESIGN decoder (low, medium, high : input; highest_level[3. . 0] : output; ) variable code[2. . 0] : node; begin code 2=high; code 1=medium; code 0=low; case code[] is when 4 => highest_level[] = B” 1000”; when 2 => highest_level[] = B” 0100”; when 1 => highest_level[] = B” 0010”; when others => highest_level[] = B” 0001”; end case; end; Copyright © 1997 Altera Corporation 注意这一行的用法

Copyright © 1997 Altera Corporation

循环语句FOR. . . LOOP. . . CONSTANT num_of_bit = 8; SUBDESIGN numbit ( a[num_of_bit. . 0] : input; b[num_of_bit. . 0] : output; ) begin b[8] = a[0]; b[7] = a[1]; b[6] = a[2]; 实现相同的功能更加容易 b[5] = a[3]; b[4] = a[4]; b[3] = a[5]; b[2] = a[6]; b[1] = a[7]; b[0] = a[8]; end; Copyright © 1997 Altera Corporation CONSTANT num_of_bit = 8; SUBDESIGN numbit ( a[num_of_bit. . 0] : input; b[num_of_bit. . 0] : output; ) begin for i in 0 to num_of_bit generate b[num_of_bit - i] = a[i]; end generate; end; CONSTANT num_of_bit = 8; SUBDESIGN numbit (a[num_of_bit. . 0] : input; b[num_of_bit. . 0] : otuput; ) begin b[num_of_bit. . 0] = a[0. . num_of_bit]; end;

寄存器逻辑的实现 方法 1 SUBDESIGN flip_flop ( d, clk : input; q : output; ) begin q = dff(d, clk, , ); end; Copyright © 1997 Altera Corporation 方法 2 SUBDESIGN flip_flop ( d, clk : input; q : output; ) variable temp : dff; begin temp. d = d; temp. clk = clk; q = temp. q; end; 调用一个 D-Flipflop

更详细的说明 Copyright © 1997 Altera Corporation

总线寄存器的实现 SUBDESIGN bus_reg ( clk, d[7. . 0] : input; q[7. . 0] : output; ) variable ff[7. . 0] : dff; begin ff[]. clk = clk; ff[]. d = d[]; q[] = ff[]. q; end; Copyright © 1997 Altera Corporation q[0] = ff[0]. q; q[1] = ff[1]. q; q[2] = ff[2]. q; q[3] = ff[3]. q; q[4] = ff[4]. q; q[5] = ff[5]. q; q[6] = ff[6]. q; q[7] = ff[7]. q; ff[0]. d = d[0]; ff[1]. d = d[1]; ff[2]. d = d[2]; ff[3]. d = d[3]; ff[4]. d = d[4]; ff[5]. d = d[5]; ff[6]. d = d[6]; ff[7]. d = d[7]; ff[0]. clk = clk; ff[1]. clk = clk; ff[2]. clk = clk; ff[3]. clk = clk; ff[4]. clk = clk; ff[5]. clk = clk; ff[6]. clk = clk; ff[7]. clk = clk;

带清零端、预置端和使能端的D触发器 SUBDESIGN flip_flop_enable (( clock, data, enable, preset, clear : : input; qout : : output; )) variable temp : : dffe; begin temp. d == data; temp. clk == clock; temp. clrn = clear; temp. prn == preset; temp. ena == enable; qout == temp. q; end; Copyright © 1997 Altera Corporation PRN PRN Q Q D D CLK CLK ENA ENA CLRN

其他类型的触发器 Copyright © 1997 Altera Corporation

帮助菜单的使用 Copyright © 1997 Altera Corporation

三态缓冲器的实现 方法 1 方法 2 SUBDESIGN tri_state (a, enable : input; b : output; ) begin b = tri(a, enable); end; SUBDESIGN tri_state ( a, enable : input; b : output; ) variable temp : tri; begin temp. in = a; temp. oe = enable; b = temp. out; end; Copyright © 1997 Altera Corporation

更详细的说明 Copyright © 1997 Altera Corporation

OPNDRN －漏极开路缓冲器 Method 1 SUBDESIGN opn_drn (enable : input; b : output; ) begin b = opndrn(enable); end; Copyright © 1997 Altera Corporation Method 2 SUBDESIGN tri_state ( enable : input; b : output; ) variable temp : opndrn; begin temp. in= enable; b = temp. out; end;

更详细的说明 Copyright © 1997 Altera Corporation

使用 AHDL 与使用原理图同样方便 但是 AHDL 功能更强大 Copyright © 1997 Altera Corporation

练习部分 AHDL 输入引脚 clk, enable : input; io : bidir; Copyright © 1997 Altera Corporation 双向引脚 SUBDESIGN tri_io ( clk, enable : input; io : bidir; ) variable temp 1 : dff; temp 2 : tri; begin temp 1. d = io; temp 1. clk = clk; temp 2. in = temp 1. q; temp 2. oe = enable; io = temp 2. out; end;

轻松地设计一个 8位计数器 SUBDESIGN 8 bits (clk : input; q[7. . 0] : output; ) variable temp[7. . 0] : dff; begin temp[]. clk = clk; temp[]. d = temp[]. q +1 ; q[] = temp[]. q; end; Copyright © 1997 Altera Corporation

状态机设计 状态转移图 jump=0 q=0 S 0 jump=1 S 1 q=1 jump=0 Copyright © 1997 Altera Corporation SUBDESIGN simple ( clk, reset, jump : input; q : output; ) variable ss : MACHINE WITH STATES (S 0, S 1); begin ss. clk = clk; ss. reset = reset; 注 : 所有的状态机都必须受时钟驱动 case ss is when s 0 => q = gnd; if (jump) then ss = s 1; end if; when s 1 => q = vcc; if (jump) then ss = s 0; end if; end case; end;

状态转移波形图 if (jump) then ss = s 1; end if; Copyright © 1997 Altera Corporation if (jump) then ss = s 0; end if;

状态机设计的其他问题 SUBDESIGN stepper ( reset, ccw, clk : input; phase[3. . 0] : output; ) variable ss : MACHINE OF BITS (temp[3. . 0]) WITH STATES ( s 0 = B” 0001”, s 1 = B” 0010”, s 2 = B” 0100”, s 3 = B” 1000”); begin ss. clk = clk; if (reset) then ss = s 2; end if; phase[] = temp[]; TABLE ss, ccw, s 0, 1, s 0, x, s 1, 1, s 1, x, s 2, 1, s 2, x, s 3, 1, s 3, x, END TABLE; end; 注 : 不必对 TEMP进行声明 它会自动声明为D触发器 Copyright © 1997 Altera Corporation cw x 1 x 1 => => => ss; s 3; s 1; s 0; s 2; s 1; s 3; s 2; s 0;

状态转移图 用户可以控制初始状态 Copyright © 1997 Altera Corporation

练习题 SUBDESIGN stepper ( reset, ccw, clk : input; phase[3. . 0] : output; ) variable ss : MACHINE OF BITS (temp[3. . 0]) WITH STATES ( s 0 = B” 0001”, s 1 = B” 0010”, s 2 = B” 0100”, s 3 = B” 1000”); begin ss. clk = clk; if (reset) then ss = s 2; end if; phase[] = temp[]; TABLE ss, ccw, s 0, 1, s 0, x, s 1, 1, s 1, x, s 2, 1, s 2, x, s 3, 1, s 3, x, END TABLE; end; 试着修改CASE语句的真值表 Copyright © 1997 Altera Corporation cw x 1 x 1 => => => ss; s 3; s 1; s 0; s 2; s 1; s 3; s 2; s 0;

没有恢复状态的状态机 SUBDESIGN recover ( clk, go : input; ok : output; ) variable sequence : MACHINE OF BITS (q[2. . 0]) with STATES ( idle, one, two, three, four, illegal 1, illegal 2, illegal 3); begin sequence. clk = clk; case sequence is when idle => if (go) then sequence = one; end if; when one => sequence = two; when two => sequence = three; when three => sequence = four; end case; ok = (sequence == four); end; 状态机停留在状态“ FOUR”上面 Copyright © 1997 Altera Corporation

状态机最好具有自启动功能 SUBDESIGN recover 三比特实现八个状态 ( clk, go : input; ok : output; ) variable sequence : MACHINE OF BITS (q[2. . 0]) with STATES ( idle, one, two, three, four, illegal 1, illegal 2, illegal 3); begin 只有五个状态有用时， sequence. clk = clk; 最好使用自启动选项 case sequence is when idle => if (go) then sequence = one; end if; when one => sequence = two; when two => sequence = three; when three => sequence = four; when OTHERS => sequence = idle; end case; ok = (sequence == four); end; Copyright © 1997 Altera Corporation