Address Decoding for Memory and IO 9206 Lecture

Address Decoding for Memory and I/O 9/20/6 Lecture 3 - Instruction Set - Al 1

Address Decoding o Address Decoding Designs n n n o Implementation n 9/20/6 Full Address Decoding Partial Address Decoding Block Address Decoding Random, Decoders, PROM, FPGA Lecture 3 - Instruction Set - Al 2

Address Decoding o o 9/20/6 Required for a microcomputer where memory and I/O support are essential Needed for embedded system when on chip microcontroller memory is not sufficient Lecture 3 - Instruction Set - Al 3

The Memory Space o 2 basic approaches n Memory mapped system – main memory and I/O space are just different addresses or regions – or memory mapped I/O (MMIO) o o n Port Mapped I/O – have unique pins (signals) that differentiate memory and I/O address spaces o o 9/20/6 Addressing is the same pins for memory and I/O Advantage – less pin and hardware complexity Advantage – If limited memory, memory is memory Advantage – Large I/O space Lecture 3 - Instruction Set - Al 4

Other architectures o Harvard Architecture n n n o 9/20/6 Separate memory spaces for instructions and data Requires pin(s) to differentiate I/O is MMIO Check these out on www. wikipedia. com Lecture 3 - Instruction Set - Al 5

The 68000 Memory Space o 23 address lines n o 9/20/6 223 words with UDS* and LDS* This is 8 M words or 16 M bytes Lecture 3 - Instruction Set - Al 6

Address Map o o 9/20/6 When implementing a system the designer creates a memory map. Map would include where RAM, ROM and I/O are. Lecture 3 - Instruction Set - Al 7

Full address decoding o 9/20/6 Each addressable location within the memory components responds to only a single unique address. Lecture 3 - Instruction Set - Al 8

Example of full address decoding 9/20/6 Lecture 3 - Instruction Set - Al 9

Ex continued 9/20/6 Lecture 3 - Instruction Set - Al 10

Partial Address Decoding o o o 9/20/6 Some of address lines are unused Least complex and most inexpensive Each component will actually respond to several addresses Lecture 3 - Instruction Set - Al 11

Partial Address decoding example 9/20/6 Lecture 3 - Instruction Set - Al 12

Block Address decoding o o o 9/20/6 Compromise between full and partial. Don’t decode all of address lines but do decode more than the bare minimum. Less repeated addresses for each populated device Lecture 3 - Instruction Set - Al 13

Designing the decode logic o o 9/20/6 Multiple methods of implementing the decode logic One method is of course to implement it with “random logic” – i. e. , AND gates, OR gates, inverters, NAND gates, NOR gates Advantage – speed Disadvantage – possibly the number of chips Lecture 3 - Instruction Set - Al 14

Decoders o o 9/20/6 USE m-line-to-n-line decoders Decode an m-bit input into one of n outputs where n = 2 m Popular 74 LS 138 – 3 -to-8 decoder Another 74 LS 154 – 4 -to-16 decoder Lecture 3 - Instruction Set - Al 15

Decoder Truth table 9/20/6 Lecture 3 - Instruction Set - Al 16

Example of decoder use 9/20/6 Lecture 3 - Instruction Set - Al 17

Implementation 9/20/6 Lecture 3 - Instruction Set - Al 18

PROMS o o 9/20/6 A PROM can also be use to implement logic functions Can use it to do address decoding Lecture 3 - Instruction Set - Al 19

Example of PROM use o 9/20/6 Decoder design must be cheap and versitle. Lecture 3 - Instruction Set - Al 20

PROM Programming 9/20/6 Lecture 3 - Instruction Set - Al 21

PROM System o Advantagen n 9/20/6 Ability to select blocks of differing size Versitility Lecture 3 - Instruction Set - Al 22

FPGA, PLA, PAL o Programmable Logic Arrays n o Programmable Array Logic n o 9/20/6 AND plane – OR plane Limited PLA FPGA – A network of CLBs Lecture 3 - Instruction Set - Al 23

PAL vs PLA o o 9/20/6 In a PAL the ouput’s connection to product terms is fixed More limited logic equation support Lecture 3 - Instruction Set - Al 24

Special devices o o 9/20/6 There also special chips specifically designed for address decoding Some may be designed for a specific family of chips Lecture 3 - Instruction Set - Al 25