Accellera Systems Initiative Update Dennis Brophy Vice Chair

Accellera Systems Initiative Update Dennis Brophy, Vice Chair | April 9, 2012

Thanks to Our Global Sponsors 2 © 2012 Accellera Systems Initiative, Inc.

Accellera and OSCI Merge “Our new organization will leverage the excellent work of our technical committees to provide a bigger benefit to the electronics industry. By forming a combined organization, we will be able to accelerate development of system level standards that will move electronic design productivity to the next level. ” Shishpal Rawat, Accellera Systems Initiative Chair 3 © 2012 Accellera Systems Initiative, Inc. April 9, 2012

Accellera Systems Initiative Our Mission § To provide design and verification standards required by systems, semiconductor, IP and design tool companies to enhance a front-end design automation process. § To collaborate with its community of companies, individuals and organizations in delivering the standards that lower the cost to design commercial EDA, IC and embedded system solutions. 4 © 2012 Accellera Systems Initiative, Inc. April 9, 2012

Merger Update § Integration of Accellera and OSCI Organizations - WIP - Ongoing review of operational procedures and policies - Leveraging strengths from both organizations to expand applicability and increase adoption - Focused on next generation of EDA and IP standards § Continue to providing free downloads of IEEE standards - IEEE 1666 System. C available since mid-January - IEEE 1685 IP-XACT downloads going strong § New Technical Excellence Award Program Launched - Candidates peer-nominated from across the organization - Recognizes work by people across multiple Accellera Systems Initiative standards 5 © 2012 Accellera Systems Initiative, Inc. April 9, 2012

Accellera Systems Initiative - Integration § Organizational Structure in Review - Procedures and Policies - IP Rights - Web Infrastructure, User forums § Expanding DVCon as “the” premier conference addressing functional design and verification - Accellera Systems Initiative Day Monday Feb. 27 th - Full conference registration & Monday tutorial attendance up from last year § Expanding Global Sponsorship Program - Opportunity for multiple companies to co-sponsor our events - Videos of all DVCon Monday tutorials and NASCUG meeting will be available on www. accellera. org 6 © 2012 Accellera Systems Initiative, Inc. April 9, 2012

IEEE 1666 System. C Downloads • 47, 165 downloads of IEEE 1666 -2005 through January 2012 • 5, 158 downloads of IEEE 1666 -2011 from January 11 through March 31 http: //standards. ieee. org/getieee/1666/download/ 1666 -2011. pdf 7 © 2012 Accellera Systems Initiative, Inc. April 9, 2012

IEEE 1685 IP-XACT Downloads Cumulative Downloads 6000 5000 4000 3000 2000 1495 1726 2007 2268 2477 2705 2960 3138 3395 3726 3999 4247 4429 4712 4927 5117 1000 M ar b Fe n 12 ec Ja D ov N ct O Se pt st gu ly Au Ju Ap r M ay Ju ne M ar b Fe 20 10 Ja n 11 0 2010 -2012 http: //standards. ieee. org/getieee/1685/download/ 1685 -2009. pdf 8 © 2012 Accellera Systems Initiative, Inc. April 9, 2012

2012 Technical Excellence Award John Aynsley § For his dedication to the System. C language and community. § His contributions span the full range of System. C language, transaction-level modeling and configuration. § Instrumental in the various working groups converging on technically sound solutions. 9

Also known as… 10 © 2011 -2012 Accellera Systems Initiative, Inc.

System. C Users Scope Expands § Unified Coverage Interoperability Standard § Universal Verification Methodology (UVM) 2. 0 § Verilog and System. C Analog/Mixed-Signal (AMS) § IP-XACT and System RDL 11 © 2012 Accellera Systems Initiative, Inc. April 9, 2012

System. C AMS 2. 0 Draft Standard Now Open for Public Review § Standard addresses dynamic and reactive mixed-signal system design § Language Reference Manual available for public review at accellera. org § Draft features additional semantics and language constructs and introduces dynamic features to the Timed Data Flow (TDF) - model of computation - abstract modeling style introduced in System. C AMS § Review open until April 30, 2012 12 © 2012 Accellera Systems Initiative, Inc. April 9, 2012

Technical Video Tutorials Available Online TLM-2. 0 Standard and Synthesizable Subset John Aynsley, Doulos; Michael Mc. Namara, Cadence; Michael Meredith, Forte TLM-2. 0 in Action: An Example-based Approach to TLM and the New World of Model Interoperability John Aynsley, Doulos; David Black, Xtreme. EDA Zhu Zhou, Intel; Frank Schirrmeister, Synopsys Using TLM Extensions for Bus Locking and Snooping John Aynsley, Doulos And More! Available at: http: //www. accellera. org/news/videos/ 13

Summary § Organizational Structure Refinement in Progress § Standards Unite Under One Roof! Expanded Scope for all in Combined Organization - Unified Coverage Interoperability Standard - Universal Verification Methodology (UVM) 2. 0 - Verilog and System. C Analog/Mixed-Signal (AMS) - IP-XACT and System RDL § System. C AMS 2. 0 Draft Standard Now Open for Public Review - Share your feedback! § Technical Tutorials and Users Presentations Available Online at no cost to users www. accellera. org 14 © 2012 Accellera Systems Initiative, Inc. April 9, 2012

Backup 15 © 2012 Accellera Systems Initiative, Inc. April 9, 2012

Accellera Systems Initiative Board of Directors Shishpal Rawat, Intel Marketing Committee Thomas Li, Springsoft Interface (ITC) Brian Bailey EDA Design. Line IP Tagging Kathy Werner Freescale Technical Committee Karen Pieper, Tabula Verilog-AMS Sri Chandra Freescale OVL Kenneth Larson Mentor Graphics VIP Hillel Miller Freescale Tom Alsop Intel IP-XACT Rohit Jindal STMicrosystems Administration System. C Synthesis Andres Takach Calypto UCIS Richard Ho DE Shaw System. C TLM Bart Vanthournout Synopsys System. C AMS Martin Barnasconi NXP Supported IEEE Working Groups 1076 VHDL Jim Lewis Synth. Works 16 1800 System. Verilog Karen Pieper Tabula © 2012 Accellera Systems Initiative, Inc. 1801 UPF John Biggs ARM April 9, 2012 1666 System. C Stan Krolikoski Cadence System. C Language David Black Doulos System. C CCI Trevor Wieman Intel

Ongoing Technical Activities Current Standards • • • • Verification Intellectual Property (VIP) Universal Verification Methodology (UVM) 1. 1 Open Verification Library (OVL) 2. 6 Verilog-AMS (V-AMS) 2. 3. 1 Standard Co-Emulation Modeling Interface (SCE-MI) 2. 1 Unified Coverage Interoperability Standard (UCIS) 1. 0 (imminent) IP-XACT (Q 1 2012) Intellectual Property (IP) Tagging (launched) System. C Synthesizable Subset Draft 1. 3 System. C Analog Mixed-Signal (AMS) 1. 0 System. C Configuration, Control & Inspection (CCI Requirements) System. C Language Standard Transaction Level Modeling (TLM) 1. 0 and 2. 0 Open Source Companions: - UVM Reference Implementation 1. 1 - System. C Proof of Concept Library (POCL) - System. C Verification Library 1. 0 p 2 17 9©th 2011 -2012 Annual DVCon – Our flagship conference Accellera Systems Initiative, Inc.

Acronyms & Definitions § AMS: Analog/Mixed Signal § CCI: Configuration, Control & Inspection § DVCon: Design & Verification Conference § EDA: Electronic Design Automation § GET: Free IEEE LRM download program § IC: Integrated Circuit § IP: Intellectual Property § IPR: Intellectual Property Rights § IP-XACT: Metadata standard for IP integration § IEEE: Institute of Electrical and Electronics Engineers § ITC: Interface Technical Committee § LWG: Language Working Group § OCI: Open Compression Interface § OSCI: Open System. C Initiative © 2012 Accellera Systems Initiative, Inc. 18 § OVI: Open Verilog International § PSL: Property Specification Language § SDF: Standard Delay Format § SC: System. C § SCV: System. C Verification § SPIRIT: Structure for Packaging, § § § § § Integrating, and Reusing IP within Toolflows SV: System. Verilog SWG: Synthesis Working Group TLM: Transaction-Level Modeling UCIS: Unified Coverage Interoperability Standard UPF: Unified Power Format UVM: Universal Verification Methodology V-AMS: Verilog-Analog/Mixed Signal VHDL: VHSIC Hardware Description Language VI: VHDL International April 9, 2012 VIP: Verification Intellectual Property