About radiation hardness 1 In the CDR Because

About radiation hardness (1) In the CDR: « Because of the very high event rates anticipated, it will be important to push as much of the task of feature extraction as possible into intelligence in the front-end electronics » . Particles (especially neutrons) above a few Me. V may interact with silicon. Neutron flux (produced by particles hitting something massive) should be directly linked to luminosity (we hope anyway to have a lumi term ~10% of BABAR’s). • The upgrade of Ba. Bar drift chamber electronics showed that putting intelligence inside this detector pushes to take the radiation problems into account. • Single Events and total dose are the two subjects of concern. • It looks like, besides SVT, total dose should not be a main worry, except maybe for in-detector electronics making use of voltage regulators. • Single Events can be split into two families: – Single Event Upsets: non destructive. May happen in the memory cells, and thus mainly concern event data and the configuration of FPGAs. – Single Event Latchup: potentially destructive. Needs higher energy. – If simulations (to be performed) show that the SEU rates may be high, our electronics has to be mitigated for it. – If SEL may occur, all used circuits have to be validated for this kind of environment (already validated COTS, beam test self-validation, …). But the probability seems rather low for Super. B.

About radiation hardness (2) Sensitivity to Single Events rapidly increases when silicon technology gets smaller. Mitigation methods depend on the expected rate of SEUs: • If the rate is low, standard FPGA can be used – Mitigation must concern both user data and configuration: • Concerning configuration, the latter has to be checked regularly and reloaded if a bit flip was detected (=> source of deadtime !) • Concerning user data, TMR (triple modular redundancy) methods can be used in the FPGA code, as well as encoded redundancy in the RAMs. • If the rate is higher, radiation tolerant families have to be used (like ACTEL’s EEPROM based Pro. Asic FPGAs). We need simulations to get a better idea of the radiation levels in order to make a safe decision on these points at an early stage of the design.