ABC A System for Sequential Synthesis and Verification

ABC: A System for Sequential Synthesis and Verification BVSRC Berkeley Verification and Synthesis Research Center University of California, Berkeley Alan Mishchenko

Overview • Introduction – What and why ABC? • ABC fundamentals – Areas addressed by ABC • Synthesis • Technology mapping • Verification – Contrast with classical methods • How is ABC different from SIS? • Recent work – – – Speedup Factoring Don’t-care based optimization Scalable sequential synthesis Wire. Map White boxes

A Plethora of ABCs http: //en. wikipedia. org/wiki/Abc • ABC (American Broadcasting Company) – A television network… • ABC (Active Body Control) – ABC is designed to minimize body roll in corner, accelerating, and braking. The system uses 13 sensors which monitor body movement to supply the computer with information every 10 ms… • ABC (Abstract Base Class) – In C++, these are generic classes at the base of the inheritance tree; objects of such abstract classes cannot be created… • ABC (supposed to mean “as simple as ABC”) – A system for sequential synthesis and verification at Berkeley

Why We Decided to Build ABC • SIS – Outdated, but many research papers on how a new algorithm beats SIS results – Not supported • MVSIS – – – Gave us a reason to work on logic synthesis Learned a lot about new methods and better data structures Could see how specializing to binary could provide substantial improvements. • ABC – Initial intention was to re-implement all algorithms using new data structures (daunting task) – Discovered rewriting AIGs • P. Bjesse and A. Boralv, "DAG-aware circuit compression formal verification", Proc. ICCAD ’ 04, pp. 42 -49. – Decided to try to keep all transformations fast and scalable • • • No BDDs No SOPs No Espresso BDD

What Is Berkeley ABC? • A system for logic synthesis and verification – – Fast Scalable Good quality of results Exploits synergy between synthesis and verification • A programming environment – Open-source – Evolving and improving over time

Design Flow System Specification RTL Logic synthesis Technology mapping Physical synthesis Manufacturing Verification ABC

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Terminology • Logic function (e. g. F = ab+cd) – Variables (e. g. b) – Minterms (e. g. abcd) – Cube (e. g. ab) • Logic network – – – Primary inputs/outputs Logic nodes Fanins/fanouts Transitive fanin/fanout cone Cut and window (defined later) Primary outputs TFO Fanouts Fanins TFI Primary inputs

Areas Addressed by ABC • Combinational synthesis – – – AIG rewriting technology mapping resynthesis after mapping • Sequential synthesis – – – retiming structural register sweep merging seq. equiv. nodes • Formal verification – – combinational equivalence checking bounded sequential verification unbounded sequential verification equivalence checking using synthesis history

Combinational Synthesis • AIG rewriting minimizes the number of AIG nodes without increasing the number of AIG levels Rewriting AIG subgraphs • Pre-computing AIG subgraphs Rewriting node A – Consider function f = abc Subgraph 1 Subgraph 2 A A a b Subgraph 3 a c b a c Subgraph 2 Subgraph 1 Rewriting node B a a b a c b b c B a c a a b a c b B c Subgraph 2 a b a c Subgraph 1 In both cases 1 node is saved

Technology Mapping Input: A Boolean network (And-Inverter Graph) Output: A netlist of K-LUTs implementing AIG and optimizing some cost function f f Technology Mapping a b c d e The subject graph a b c d e The mapped netlist

Sequential Synthesis • Structural register sweep (scl) – Merge registers with identical drivers – Replace stuck-at registers by constants • Retiming (dretime) – Minimize the number of registers under delay constraints – Preserves equivalent initial state • Sequential SAT sweeping (scorr) – Detecting and merging sequentially equivalent nodes

Formal Verification • Equivalence checking – Takes two designs and makes a miter (AIG) • Model checking safety properties – Takes design and property and makes a miter (AIG) 0 D 2 D 1 Property checking p The goals are the same: to transform AIG until the output is proved constant 0 0 D 1

ABC vs. Other Tools § Industrial + well documented, fewer bugs - black-box, push-button, no source code, often expensive § SIS + traditionally very popular - data structures / algorithms outdated, weak sequential synthesis § VIS + very good implementation of BDD-based verification algorithms - not meant for logic synthesis, does not feature the latest SAT-based implementations § MVSIS + allows for multi-valued and finite-automata manipulation - not meant for binary synthesis, lacking recent implementations

How Is ABC Different From SIS? Boolean network in SIS Equivalent AIG in ABC f f z z x y e a b c d AIG is a Boolean network of 2 -input AND nodes and invertors (dotted lines)

One AIG Node – Many Cuts Combinational AIG • Manipulating AIGs in ABC f – – – Each node in an AIG has many cuts Each cut is a different SIS node No a priori fixed boundaries • Implies that AIG manipulation with cuts is equivalent to working on many Boolean networks at the same time a b c d e Different cuts for the same node

Comparison of Two Syntheses ABC “contemporary” synthesis “Classical” synthesis • AIG network • Boolean network • DAG-aware AIG rewriting (Boolean) • Network manipulation – Several related algorithms (algebraic) • Rewriting – Elimination • Refactoring – Factoring/Decomposition • Balancing • Speedup – Speedup • Node minimization – Boolean decomposition – Espresso – Don’t cares computed using simulation and SAT BDDs – Resubstitution with don’t cares – Resubstitution • Technology mapping – Tree based – Cut based with choice nodes

Existing Capabilities (2005 -2008) Technology mapping with structural choices Combinational logic synthesis Cut-based, heuristic, good area/delay, flexible Fast, scalable, good quality ABC Sequential verification Sequential synthesis Integrated, interacts with synthesis Innovative, scalable, verifiable

Overview • Introduction – What is ABC? • ABC fundamentals – Areas addressed by ABC • • • Synthesis Technology mapping Verification – Contrast with classical methods • How is ABC different from SIS? • Recent work – – – Speedup Factoring Don’t-care based optimization Scalable sequential synthesis Wire. Map White boxes • Summary

Command “speedup” Timing Criticality • Critical nodes Primary outputs – Used by many traditional algorithms • Critical edges 4 4 – Used by our algorithm 3 • We pre-compute critical edges of critical nodes 2 – Reduces computation • An edge between critical nodes may not be critical – See illustration: edge 1 3 3 1 Primary inputs 2 1

Delay-Oriented Restructuring • Using traditional MUX-restructuring – AKA generalized select transform x and y are the critical edge inputs

Overall Algorithm mapped netlist perform. Speedup ( subject graph S, // S is an And-Inverter Graph mapped netlist M, // M was previously derived by tech-mapping of S timing window w, // w is used to detect the critical paths logic depth l, // l is used to detect a logic cone rooted at a node edge count p ) // p limits the number critical edges of the cone { Done only once perform timing analysis of M with unit-delay or LUT-library model; pre-compute critical section of M as nodes n such that 0 slack(n) w; pre-compute timing-critical edges connecting these nodes; for each timing critical node n { find cone C of M that extends l levels down from n; pick the set of timing-critical edges V feeding into C; if the number of edges in V exceeds p, continue; find logic cone C’ in S corresponding to C in M; find variables V’ in S corresponding to V in M; derive cofactors of the function of C’ w. r. t. variables in V’; build multiplexer tree C’’ of the cofactors using variables in V’; add structural choice C’= C’’ to the subject graph S; } return mapped netlist M’ derived by mapping subject graph S with added choices; }

Experimental Results for “speedup” LUT – number of LUTs Lev – number of LUT levels Delay – delay using LUT library Total – total runtime of Baseline Time 1 – the runtime of AIG restructuring only Time 2 – the total runtime of Speedup Geomean – geometric averages of columns Ratios – ratios of geometric averages

Overview • Introduction – What is ABC? • ABC fundamentals – Areas addressed by ABC • • • Synthesis Technology mapping Verification – Contrast with classical methods • How is ABC different from SIS? • Recent work – – – Speedup Factoring Don’t-care based optimization Scalable sequential synthesis Wire. Map White boxes • Summary

Basic Inner Core Algorithm (DSD) We use a fast disjoint support decomposition (DSD) algorithm as our underlying subroutine – follows Bertacco and Damiani, "The disjunctive decomposition of logic functions“, ICCAD '97 – but • uses heuristics to speed it up • no BDDs • uses truth tables – limit inputs to up to 16 BDD

Disjoint Support Decomposition (DSD) (Simple Disjunctive Decomposition) Theorem 1 [Ashenhurst 1959]. For a completely specified Boolean function, there is a unique maximal DSD (up to the complementation of inputs and outputs and factoring of ANDs/ORs and XORs). E 1 F D a c a H C D c A x 1 G x 3 B x 2 x 4 x 5

Non-Disjoint Decomposition Definition: A function F has an ( )decomposition if it can be written as where ( ) is a partition of the variables x and D is a single output function. H The variables in the set b are called the shared variables. The variables a are called the bound set and c the free set. 1 c D a b

Non-Disjoint Decomposition Theorem 2: A function has an decomposition if and only if each of the cofactors of F with respect to has a DSD structure in which the variables are in a separate sub-tree. E X Z W x 5 C Y x 4 D x 2 x 1 A x 4 G x 1 B x 5 x 2 x 3

Application of Factoring (uses Theorem 2) Rewriting a k-LUT mapped circuit. • For each LUT, and each cut of no more than 16 inputs, – express the output of the LUT as truth table in terms of the cut variables – F(x) – Find variables b such that its cofactors are support reducing • we exhaustively look for up to two variables in the b set – Take the best (a, b) set and decompose F=H(D(a, b), b, c) – Recursively decompose H and D if they do not fit into a k-LUT. – If improvement, replace LUTs in cut with its new decomposition. Experimental results later

Overview • Introduction – What is ABC? • ABC fundamentals – Areas addressed by ABC • • • Synthesis Technology mapping Verification – Contrast with classical methods • How is ABC different from SIS? • Recent work – – – Speedup Factoring Don’t-care based optimization Scalable sequential synthesis Wire. Map White boxes • Summary

Windowing a Node in the Network for Don’t-Care Computation • Definition Boolean network (k-LUT mapped circuit) – A window for a node in the network is the context in which the don’t-cares are computed • A window includes – – – n levels of the TFI m levels of the TFO all re-convergent paths captured in this scope • Window with its PIs and POs can be considered as a separate network Window POs m=3 n=3 Window PIs

Care Set Representation “Miter” constructed for the window POs If output is 1 then we care … Window f f x x s Same window with inverter

Resubstitution considers a node in a Boolean network and expresses it using a different set of fanins X X Computation can be enhanced by use of don’t cares

Resubstitution with Don’t-Cares Consider all or some nodes in Boolean network. For each node • Create window • Select possible fanin nodes (divisors) • For each candidate subset of divisors – – – Rule out some subsets using simulation Check resubstitution feasibility using SAT Compute resubstitution function using interpolation • A low-cost by-product of completed SAT proofs • Update the network if there is an improvement

Resubstitution with Don’t Cares • Given: – node function F(x) to be replaced – care set C(x) for the node – candidate set of divisors {gi(x)} for reexpressing F(x) C(x) F(x) • Find: F’(x) – A resubstitution function h(y) such that F(x) = h(g(x)) on the care set C(x) F(x) • SPFD Theorem: Function h exists if and only if every pair of care minterms, x 1 and x 2, distinguished by F(x), is also distinguished by gi(x) for some i g 1 g 2 g 3 h(g) g 1 g 2 g 3

Checking Resubstitution using SAT Miter for resubstitution check SPFD theorem in practice h (g ) F F 1. Note use of care set, C. 2. Resubstitution function exists if and only if SAT problem is unsatisfiable. 3. An h(g) is obtained by interpolation

Experimental Results

Overview • Introduction – What is ABC? • ABC fundamentals – Areas addressed by ABC • Synthesis • Technology mapping • Verification – Contrast with classical methods • How is ABC different from SIS? • Recent work – – – Speedup Factoring Don’t-care based optimization Scalable sequential synthesis Wire. Map White boxes • Summary

The Main Idea • Consider registers and nodes of a design – Detect candidate equivalences in this set using random/guided simulation – Prove candidates by K-step induction – Merge the resulting equivalences • This is a subset of sequential synthesis with – – Practical advantages (does not move registers, etc) Scales to large designs Offers substantial improvements Comes with a verification guarantee

Base Case Inductive Case Candidate equivalences: {A, B}, {C, D} ? SAT-2 ? SAT-4 D ? ? C D D ? C SAT-1 A B PIk D SAT-2 C 0 SAT-3 A B PI 1 PI 0 Proving internal equivalences in a topological order in frame K ? SAT-1 A B Assuming internal equivalences to in uninitialized frames 0 through K-1 C A 0 B PI 1 D Initial state Proving internal equivalences in initialized frames 0 through K-1 0 0 C A PI 0 B Symbolic state

Dynamic Partitioning (register correspondence) ? A’ = B’ Illustration for two candidate equiv. classes: {A, B}, {C, D} Partition 1 A =B A’ B’ C’ D’ ? C’ = D’ One time-frame of the design A B C D Partition 2 A =B C =D

Academic Benchmarks Columns “Baseline”, “Reg Corr” and “Sig Corr” show geometric means.

Industrial Benchmarks In case of multiple clock domains, optimization was applied only to the domain with the largest number of registers.

Reasons for Large Improvements • • Redundancy introduced by HDL compilers Early logic duplication by the designer Accidental sequential redundancies Sequential redundancies present due to reuse of design components that had more functionality than needed

Overview • Introduction – What is ABC? • ABC fundamentals – Areas addressed by ABC • • • Synthesis Technology mapping Verification – Contrast with classical methods • How is ABC different from SIS? • Recent work – – – Speedup Factoring Don’t-care based optimization Scalable sequential synthesis Wire. Map White boxes • Summary

Motivation • Fewer pin-to-pin connections should make the design easier to place and route • Newer FPGAs allow two outputs per LUT – Thus fewer pin-to-pin connections should produce a mapping that “packs” better into dual-output LUTs

Area Recovery Overview 1. Perform delay-optimal mapping 2. Recover area off critical paths – Area-flow (global view) • Chooses cuts with better logic sharing – Exact local area (local view) Both are importa nt 3. New idea: Cut-based area recovery algorithms can be extended to minimize edges (pin-to-pin connections)

Wire. Map Algorithm 1. Perform delay-optimal mapping 2. Recover area off critical paths – Area-flow (global view) • Break ties with minimum edge flow – Exact local area (local view) • Break ties with exact local edge count

Experimental Setup • • Wire. Map implemented in ABC Compared Wire. Map against two algorithms in ABC – – • • • Baseline – basic mapping with area recovery Mapping with Structural Choices – mapping with area recovery for several netlists produced by synthesis Wire. Map was implemented on top of mapping with choices Used VPR to place/route design for wirelength and critical path delays Used maximum cardinality matching to pack singleoutput LUTs into dual-output LUTs using

Results Summary • Comparing Wire. Map against the best mapping with structural choices in ABC • Wire. Map results: – Reduction in edges by 9. 3% – Reduction in dual-output LUT count by 9. 4%, compared to mapping with choices • Single-output LUT count only reduced by 1. 3% – Reduction in wire length by 8. 5% – Reduction in power by 20%

Overview • Introduction – What is ABC? • ABC fundamentals – Areas addressed by ABC • • • Synthesis Technology mapping Verification – Contrast with classical methods • How is ABC different from SIS? • Recent work – – – Speedup Factoring Don’t-care based optimization Scalable sequential synthesis Wire. Map White boxes • Summary

Comb and Seq Boxes FF a n 1 FF 1 n 6 n 4 c FF FF 3 n 3 FF n 1 n 8 n 2 FF b o 1 FF 4 FF 5 o 2 n 7 FF Seq box FF FF o 3 FF FF b o 4 FF c Comb box Seq box n 2

Treating Boxes as Black FF a n 1 FF 1 n 6 n 4 c FF FF 3 n 3 FF n 1 n 8 n 2 FF b o 1 FF 4 FF 5 o 2 n 7 FF Seq box FF FF o 3 FF FF b n 2 o 4 FF c Comb box Seq box For simplicity, boxes can be treated as “black”. Thus box outputs become inputs to the rest of the logic and box inputs become outputs. Delay and logic information is lost.

Treating Boxes as White FF a n 1 FF 1 n 6 n 4 c FF FF 3 n 3 FF n 1 n 8 n 2 FF b o 1 FF 4 FF 5 o 2 n 7 FF Seq box FF FF o 3 FF FF b n 2 o 4 FF c Comb box Seq box Example: Nodes o 1 and o 3 may be equivalent in the design, but this equivalence cannot be detected if the boxes are treated as black. Solution: Consider logic inside white boxes for synthesis, but keep it unchanged during synthesis and mapping.

Future Work Integrating synthesis/ mapping/retiming Improving AIG-based synthesis and mapping Co-developing synthesis and verification Creating special configurable design flows ABC Integrating synthesis with place and route Supporting emerging technologies

To Learn More • Visit ABC webpage http: //www. eecs. berkeley. edu/~alanmi/abc • Read recent papers http: //www. eecs. berkeley. edu/~alanmi/publications • Send email – alanmi@eecs. berkeley. edu – brayton@eecs. berkeley. edu