A singlecycle MIPS processor As previously discussed an

A single-cycle MIPS processor As previously discussed, an instruction set architecture is an interface that defines the hardware operations which are available to software. Any instruction set can be implemented in many different ways. Over the next few weeks we’ll compare two important implementations. — In a basic single-cycle implementation all operations take the same amount of time—a single cycle. — In a pipelined implementation, a processor can overlap the execution of several instructions, potentially leading to big performance gains. 04 March 2021 1

Single-cycle implementation In lecture, we will describe the implementation a simple MIPS-based instruction set supporting just the following operations. Arithmetic: Data Transfer: Control: add sub lw sw and or slt beq — We use MIPS because it is significantly easier to implement than x 86. Today we’ll build a single-cycle implementation of this instruction set. — All instructions will execute in the same amount of time; this will determine the clock cycle time for our performance equations. — We’ll explain the datapath first, and then make the control unit. 04 March 2021 A single-cycle MIPS processor 2

Computers are state machines A computer is just a big fancy state machine. — Registers, memory, hard disks and other storage form the state. — The processor keeps reading and updating the state, according to the instructions in some program. Computers are state machines (or finite automata). CPU State 04 March 2021 A single-cycle MIPS processor 3

John von Neumann In the old days, “programming” involved actually changing a machine’s physical configuration by flipping switches or connecting wires. — A computer could run just one program at a time. — Memory only stored data that was being operated on. Then around 1944, John von Neumann and others got the idea to encode instructions in a format that could be stored in memory just like data. — The processor interprets and executes instructions from memory. — One machine could perform many different tasks, just by loading different programs into memory. — The “stored program” design is often called a Von Neumann machine. 04 March 2021 A single-cycle MIPS processor 4

Memories It’s easier to use a Harvard architecture at first, with programs and data stored in separate memories. To fetch instructions and read & write words, we need these memories to be 32 -bits wide (buses are represented by dark lines here), so these are 230 x 32 memories. (We will ignore byte addressability for the moment. ) Blue lines represent control signals. Mem. Read and Mem. Write should be set to 1 if the data memory is to be read or written respectively, and 0 otherwise. — When a control signal does something when it is set to 1, we call it active high (vs. active low) because 1 is usually a higher voltage than 0. For today, we will assume you cannot write to the instruction memory. — Pretend it’s already loaded with a program, which doesn’t change while it’s running. 04 March 2021 A single-cycle MIPS processor Read Instruction address [31 -0] Instruction memory Mem. Write Read address Read data Write address Write data Data memory Mem. Read 5

Instruction fetching The CPU is always in an infinite loop, fetching instructions from memory and executing them. The program counter or PC register holds the address of the current instruction. MIPS instructions are each four bytes long, so the PC should be incremented by four to read the next instruction in sequence. 2004 Add 2004 4 PC 2000 Read Instruction address [31 -0] Instruction memory 04 March 2021 A single-cycle MIPS processor 6

Encoding R-type instructions A few weeks ago, we saw encodings of MIPS instructions as 32 -bit values. Register-to-register arithmetic instructions use the R-type format. — op is the instruction opcode, and func specifies a particular arithmetic operation (see the back of the textbook). — rs, rt and rd are source and destination registers. op rs rt rd shamt func 6 bits 5 bits 6 bits An example instruction and its encoding: add $s 4, $t 1, $t 2 04 March 2021 000000 01001 01010 A single-cycle MIPS processor 10100 00000 1000000 7

Registers and ALUs R-type instructions must access registers and an ALU. Our register file stores thirty-two 32 -bit values. — Each register specifier is 5 bits long. — You can read from two registers at a time. — Reg. Write is 1 if a register should be written. Here’s a simple ALU with five operations, selected by a 3 -bit control signal ALUOp. 04 March 2021 ALUOp Function 000 001 010 111 and or add subtract slt A single-cycle MIPS processor Reg. Write Read register 1 Read data 1 Read register 2 Read data 2 Write register Write data Registers ALUOp 8

Executing an R-type instruction 1. Read an instruction from the instruction memory. 2. The source registers, specified by instruction fields rs and rt, should be read from the register file. 3. The ALU performs the desired operation. 4. Its result is stored in the destination register, which is specified by field rd of the instruction word. Reg. Write Read Instruction address [31 -0] I [25 - 21] I [20 - 16] Instruction memory I [15 - 11] Read register 1 Read register 2 Write register Write data op 31 04 March 2021 rs 26 25 Read data 1 20 Zero Result Read data 2 ALUOp Registers rt 21 ALU rd 16 15 shamt 11 10 A single-cycle MIPS processor 6 5 func 0 9

Encoding I-type instructions The lw, sw and beq instructions all use the I-type encoding. — rt is the destination for lw, but a source for beq and sw. — address is a 16 -bit signed constant. op rs rt address 6 bits 5 bits 16 bits Two example instructions: lw $t 0, – 4($sp) 100011 11101 01000 1111 1100 sw $a 0, 16($sp) 101011 11101 00100 0000 0001 0000 04 March 2021 A single-cycle MIPS processor 10

Accessing data memory For an instruction like lw $t 0, – 4($sp), the base register $sp is added to the sign-extended constant to get a data memory address. This means the ALU must accept either a register operand for arithmetic instructions, or a sign-extended immediate operand for lw and sw. We’ll add a multiplexer, controlled by ALUSrc, to select either a register operand (0) or a constant operand (1). r 1 M u x r 2 1 Reg. Dst 04 March 2021 r 1 0 r 1 r 2 0 M u x r 2 1 Reg. Dst A single-cycle MIPS processor 11

Accessing data memory For an instruction like lw $t 0, – 4($sp), the base register $sp is added to the sign-extended constant to get a data memory address. This means the ALU must accept either a register operand for arithmetic instructions, or a sign-extended immediate operand for lw and sw. We’ll add a multiplexer, controlled by ALUSrc, to select either a register operand (0) or a constant operand (1). Reg. Write Read Instruction address [31 -0] Mem. Write I [25 - 21] Read register 1 I [20 - 16] Instruction memory 0 M u I [15 - 11] x 1 Read data 1 Zero Read register 2 Read data 2 Write register Write data Registers Sign extend (FFFC)hex (A 37 C)hex 04 March 2021 0 M u x 1 Result ALUOp ALUSrc Reg. Dst I [15 - 0] ALU Read address Read data Write address Write data Data memory Mem. To. Reg 1 M u x 0 Mem. Read (FFFFFFFC)hex (0000 A 37 C)hex A single-cycle MIPS processor 12

Mem. To. Reg The register file’s “Write data” input has a similar problem. It must be able to store either the ALU output of R-type instructions, or the data memory output for lw. We add a mux, controlled by Mem. To. Reg, to select between saving the ALU result (0) or the data memory output (1) to the registers. Reg. Write Read Instruction address [31 -0] Mem. Write I [25 - 21] Read register 1 I [20 - 16] Instruction memory 0 M u I [15 - 11] x 1 Read register 2 Write register Write data Read data 1 Zero Read data 2 Registers 04 March 2021 0 M u x 1 Result ALUOp ALUSrc Reg. Dst I [15 - 0] ALU Read address Read data Write address Write data Data memory Mem. To. Reg 1 M u x 0 Mem. Read Sign extend A single-cycle MIPS processor 13

Reg. Dst A final annoyance is the destination register of lw is in rt instead of rd. op rs rt address lw $rt, address($rs) We’ll add one more mux, controlled by Reg. Dst, to select the destination register from either instruction field rt (0) or field rd (1). Reg. Write Read Instruction address [31 -0] Mem. Write I [25 - 21] Read register 1 I [20 - 16] Instruction memory 0 M u I [15 - 11] x 1 Read register 2 Write register Write data Read data 1 Zero Read data 2 Registers 04 March 2021 0 M u x 1 Result ALUOp ALUSrc Reg. Dst I [15 - 0] ALU Read address Read data Write address Write data Data memory Mem. To. Reg 1 M u x 0 Mem. Read Sign extend A single-cycle MIPS processor 14

Branches For branch instructions, the constant is not an address but an instruction offset from the current program counter to the desired address. L: beq add j add $at, $0, L $v 1, $v 0, $0 $v 1, $v 1 Somewhere $v 1, $v 0 The target address L is three instructions past the beq, so the encoding of the branch instruction has 0000 0011 for the address field. 000100 00001 00000 0011 op rs rt address Instructions are 4 bytes long, so the actual memory offset is 4*3=12 bytes. 04 March 2021 A single-cycle MIPS processor 15

The steps in executing a beq 1. 2. 3. 4. Fetch the instruction, like beq $at, $0, offset, from memory. Read the source registers, $at and $0, from the register file. Compare the values by subtracting them in the ALU. If the subtraction result is 0, the source operands were equal and the PC should be loaded with the target address, PC + 4 + (offset x 4). 5. Otherwise the branch should not be taken, and the PC should just be incremented to PC + 4 to fetch the next instruction sequentially. 04 March 2021 A single-cycle MIPS processor 16

Branching hardware We need a second adder, since the ALU is already doing subtraction for the beq. 0 M u x Add PC 4 Multiply constant by 4 to get offset. Add Shift left 2 1 PCSrc=1 branches to PC+4+(offset 4). PCSrc=0 continues to PC+4. PCSrc Reg. Write Read Instruction address [31 -0] Mem. Write I [25 - 21] Read register 1 I [20 - 16] Instruction memory 0 M u I [15 - 11] x 1 Read register 2 Write register Write data Read data 1 Zero Read data 2 Registers 04 March 2021 0 M u x 1 Result ALUOp ALUSrc Reg. Dst I [15 - 0] ALU Read address Read data Write address Write data Data memory Mem. To. Reg 1 M u x 0 Mem. Read Sign extend A single-cycle MIPS processor 17

The final datapath 0 M u x Add PC 4 Add Shift left 2 1 PCSrc Reg. Write Read Instruction address [31 -0] Mem. Write I [25 - 21] Read register 1 I [20 - 16] Instruction memory 0 M u I [15 - 11] x 1 Read register 2 Write register Write data Read data 1 Zero Read data 2 Registers 04 March 2021 0 M u x 1 Result ALUOp ALUSrc Reg. Dst I [15 - 0] ALU Read address Read data Write address Write data Data memory Mem. To. Reg 1 M u x 0 Mem. Read Sign extend A single-cycle MIPS processor 18

Control The control unit is responsible for setting all the control signals so that each instruction is executed properly. — The control unit’s input is the 32 -bit instruction word. — The outputs are values for the blue control signals in the datapath. Most of the signals can be generated from the instruction opcode alone, and not the entire 32 -bit word. To illustrate the relevant control signals, we will show the route that is taken through the datapath by R-type, lw, sw and beq instructions. 04 March 2021 A single-cycle MIPS processor 19

R-type instruction path The R-type instructions include add, sub, and, or, and slt. The ALUOp is determined by the instruction’s “func” field. 0 M u x Add PC 4 Add Shift left 2 1 PCSrc Reg. Write Read Instruction address [31 -0] Mem. Write I [25 - 21] Read register 1 I [20 - 16] Instruction memory 0 M u I [15 - 11] x 1 Read register 2 Write register Write data Read data 1 Zero Read data 2 Registers 04 March 2021 0 M u x 1 Result ALUOp ALUSrc Reg. Dst I [15 - 0] ALU Read address Read data Write address Write data Data memory Mem. To. Reg 1 M u x 0 Mem. Read Sign extend A single-cycle MIPS processor 20

lw instruction path An example load instruction is lw $t 0, – 4($sp). The ALUOp must be 010 (add), to compute the effective address. 0 M u x Add PC 4 Add Shift left 2 1 PCSrc Reg. Write Read Instruction address [31 -0] Mem. Write I [25 - 21] Read register 1 I [20 - 16] Instruction memory 0 M u I [15 - 11] x 1 Read register 2 Write register Write data Read data 1 Zero Read data 2 Registers 04 March 2021 0 M u x 1 Result ALUOp ALUSrc Reg. Dst I [15 - 0] ALU Read address Read data Write address Write data Data memory Mem. To. Reg 1 M u x 0 Mem. Read Sign extend A single-cycle MIPS processor 21

sw instruction path An example store instruction is sw $a 0, 16($sp). The ALUOp must be 010 (add), again to compute the effective address. 0 M u x Add PC 4 Add Shift left 2 1 PCSrc Reg. Write Read Instruction address [31 -0] Mem. Write I [25 - 21] Read register 1 I [20 - 16] Instruction memory 0 M u I [15 - 11] x 1 Read register 2 Write register Write data Read data 1 Zero Read data 2 Registers 04 March 2021 0 M u x 1 Result ALUOp ALUSrc Reg. Dst I [15 - 0] ALU Read address Read data Write address Write data Data memory Mem. To. Reg 1 M u x 0 Mem. Read Sign extend A single-cycle MIPS processor 22

beq instruction path One sample branch instruction is beq $at, $0, offset. The ALUOp is 110 (subtract), to test for equality. The branch may or may not be taken, depending on the ALU’s Zero output 0 M u x Add PC 4 Add Shift left 2 1 PCSrc Reg. Write Read Instruction address [31 -0] Mem. Write I [25 - 21] Read register 1 I [20 - 16] Instruction memory 0 M u I [15 - 11] x 1 Read register 2 Write register Write data Read data 1 Zero Read data 2 Registers 04 March 2021 0 M u x 1 Result ALUOp ALUSrc Reg. Dst I [15 - 0] ALU Read address Read data Write address Write data Data memory Mem. To. Reg 1 M u x 0 Mem. Read Sign extend A single-cycle MIPS processor 23

Control signal table Operation Reg. Dst Reg. Write ALUSrc ALUOp Mem. Write Mem. Read Mem. To. Reg add 1 1 0 010 0 sub 1 1 0 110 0 and 1 1 0 000 0 or 1 1 0 001 0 0 0 slt 1 1 0 111 0 0 0 lw 0 1 1 010 0 1 1 sw X 0 1 010 1 0 X beq X 0 0 110 0 0 X sw and beq are the only instructions that do not write any registers. lw and sw are the only instructions that use the constant field. They also depend on the ALU to compute the effective memory address. ALUOp for R-type instructions depends on the instructions’ func field. The PCSrc control signal (not listed) should be set if the instruction is beq and the ALU’s Zero output is true. 04 March 2021 A single-cycle MIPS processor 24

Generating control signals The control unit needs 13 bits of inputs. — Six bits make up the instruction’s opcode. — Six bits come from the instruction’s func field. — It also needs the Zero output of the ALU. The control unit generates 10 bits of output, corresponding to the signals mentioned on the previous page. You can build the actual circuit by using big K-maps, big Boolean algebra, or big circuit design programs. The textbook presents a slightly different control unit. Reg. Dst Reg. Write Read Instruction address [31 -0] I [31 - 26] ALUSrc ALUOp I [5 - 0] Mem. Write Control Instruction memory Mem. Read Mem. To. Reg PCSrc Zero 04 March 2021 A single-cycle MIPS processor 25

Summary A datapath contains all the functional units and connections necessary to implement an instruction set architecture. — For our single-cycle implementation, we use two separate memories, an ALU, some extra adders, and lots of multiplexers. — MIPS is a 32 -bit machine, so most of the buses are 32 -bits wide. The control unit tells the datapath what to do, based on the instruction that’s currently being executed. — Our processor has ten control signals that regulate the datapath. — The control signals can be generated by a combinational circuit with the instruction’s 32 -bit binary encoding as input. On next slides, we’ll see the performance limitations of this single-cycle machine and discuss how to improve upon it. 04 March 2021 A single-cycle MIPS processor 26

The single-cycle design from last time 0 M u x Add PC 4 Add Shift left 2 1 A control unit (not shown) generates all the control signals from the instruction’s “op” and “func” fields. PCSrc Reg. Write Read Instruction address [31 -0] Mem. Write I [25 - 21] Read register 1 I [20 - 16] Instruction memory 0 M u I [15 - 11] x 1 Read register 2 Write register Write data Read data 1 Zero Read data 2 Registers 04 March 2021 0 M u x 1 ALUSrc Reg. Dst I [15 - 0] ALU Result ALUOp Read address Read data 1 Data memory 0 Write address Write data Mem. To. Reg M u x Mem. Read Sign extend Multicycle datapath 27

The example add from last time Consider the instruction add $s 4, $t 1, $t 2. 000000 01001 010100 00000 100000 op rs rt rd shamt func Assume $t 1 and $t 2 initially contain 1 and 2 respectively. Executing this instruction involves several steps. 1. The instruction word is read from the instruction memory, and the program counter is incremented by 4. 2. The sources $t 1 and $t 2 are read from the register file. 3. The values 1 and 2 are added by the ALU. 4. The result (3) is stored back into $s 4 in the register file. 04 March 2021 Multicycle datapath 28

How the add goes through the datapath PC+4 0 M u x Add PC 4 Add Shift left 2 1 PCSrc Reg. Write Read Instruction address [31 -0] I [25 - 21] 01001 I [20 - 16] 01010 Instruction memory 0 M u I [15 - 11] x 1 10100 Mem. Write Read register 1 Read register 2 Write register Write data Read data 1 Read data 2 Registers I [15 - 0] 04 March 2021 ALU 00. . . 10 Zero 0 M u x 1 ALUSrc Reg. Dst Mem. To. Reg 00. . . 01 Sign extend Multicycle datapath Result ALUOp Read address Read data 1 Data memory 0 Write address Write data M u x Mem. Read 00. . . 11 29

Performance of Single-cycle Design CPU time. X, P = Instructions executed. P * CPIX, P * Clock cycle time. X = N 04 March 2021 * ? ? ? Performance 30

Edge-triggered state elements In an instruction like add $t 1, $t 2, how do we know $t 1 is not updated until after its original value is read? We’ll assume that our state elements are positive edge triggered, and are updated only on the positive edge of a clock signal. — The register file and data memory have explicit write control signals, Reg. Write and Mem. Write. These units can be written to only if the control signal is asserted and there is a positive clock edge. — In a single-cycle machine the PC is updated on each clock cycle, so we don’t bother to give it an explicit write control signal. CPU Reg. Write Read register 1 Read data 1 Read register 2 Read data 2 Write register Registers Write data Mem. Write Read address Read data Write address Write data Data memory Mem. Read PC State 04 March 2021 Multicycle datapath 31

The datapath and the clock 1. On a positive clock edge, the PC is updated with a new address. 2. A new instruction can then be loaded from memory. The control unit sets the datapath signals appropriately so that — registers are read, — ALU output is generated, — data memory is read or written, and — branch target addresses are computed. 3. Several things happen on the next positive clock edge. — The register file is updated for arithmetic or lw instructions. — Data memory is written for a sw instruction. — The PC is updated to point to the next instruction. In a single-cycle datapath everything in Step 2 must complete within one clock cycle, before the next positive clock edge. How long is that clock cycle? 04 March 2021 Multicycle datapath 32

Compute the longest path in the add instruction PC+4 0 M u x Add PC 4 Add Shift left 2 2 ns Reg. Write Read Instruction address [31 -0] Read register 1 I [20 - 16] 2 ns 0 M u I [15 - 11] x 1 Reg. Dst I [15 - 0] 04 March 2021 PCSrc 0 ns Mem. Write I [25 - 21] Instruction memory 1 0 ns Read data 1 Zero Read register 2 Read data 2 Write register Write data ALU Registers 0 M u x 1 Result ALUOp 2 ns 1 ns ALUSrc Sign extend 0 ns Multicycle datapath Read address Read data 1 Data memory 0 Write address Write data Mem. To. Reg M u x 0 ns Mem. Read 2 ns 33

The slowest instruction. . . If all instructions must complete within one clock cycle, then the cycle time has to be large enough to accommodate the slowest instruction. For example, lw $t 0, – 4($sp) is the slowest instruction needing __ns. — Assuming the circuit latencies below. Read Instruction address [31 -0] I [25 - 21] Read register 1 I [20 - 16] Instruction memory 2 ns 0 M u I [15 - 11] x 1 0 ns I [15 - 0] Read data 1 Zero Read register 2 Read data 2 Write register Write data ALU 0 M u x Registers 1 0 ns 1 ns Result 2 ns Read address Read data 1 Data memory 0 Write address Write data M u x 0 ns 2 ns Sign extend 0 ns 04 March 2021 Multicycle datapath 34

The slowest instruction. . . If all instructions must complete within one clock cycle, then the cycle time has to be large enough to accommodate the slowest instruction. For example, lw $t 0, – 4($sp) needs 8 ns, assuming the delays shown here. reading the instruction memory reading the base register $sp computing memory address $sp-4 reading the data memory storing data back to $t 0 Read Instruction address [31 -0] I [25 - 21] Read register 1 I [20 - 16] Instruction memory 2 ns 0 M u I [15 - 11] x 1 0 ns I [15 - 0] Read data 1 ALU Zero Read register 2 Read data 2 Write register Write data 2 ns 1 ns 0 M u x Registers 1 0 ns 1 ns Result 2 ns 8 ns Read address Read data 1 Data memory 0 Write address Write data M u x 0 ns 2 ns Sign extend 0 ns 04 March 2021 Multicycle datapath 35

. . . determines the clock cycle time If we make the cycle time 8 ns then every instruction will take 8 ns, even if they don’t need that much time. For example, the instruction add $s 4, $t 1, $t 2 really needs just 6 ns. reading the instruction memory reading registers $t 1 and $t 2 computing $t 1 + $t 2 storing the result into $s 0 Read Instruction address [31 -0] I [25 - 21] Read register 1 I [20 - 16] Instruction memory 2 ns 0 M u I [15 - 11] x 1 0 ns I [15 - 0] ns ns Read data 1 6 ns ALU Zero Read register 2 Read data 2 Write register Write data 2 1 0 M u x Registers 1 0 ns 1 ns Result 2 ns Read address Read data 1 Data memory 0 Write address Write data M u x 0 ns 2 ns Sign extend 0 ns 04 March 2021 Multicycle datapath 36

How bad is this? With these same component delays, a sw instruction would need 7 ns, and beq would need just 5 ns. Let’s consider the gcc instruction mix from p. 189 of the textbook. Instruction Frequency Arithmetic Loads Stores Branches 48% 22% 11% 19% With a single-cycle datapath, each instruction would require 8 ns. But if we could execute instructions as fast as possible, the average time per instruction for gcc would be: (48% x 6 ns) + (22% x 8 ns) + (11% x 7 ns) + (19% x 5 ns) = 6. 36 ns The single-cycle datapath is about 1. 26 times slower! 04 March 2021 Multicycle datapath 37

It gets worse. . . We’ve made very optimistic assumptions about memory latency: — Main memory accesses on modern machines is >50 ns. • For comparison, an ALU on an AMD Opteron takes ~0. 3 ns. Our worst case cycle (loads/stores) includes 2 memory accesses — A modern single cycle implementation would be stuck at <10 Mhz. — Caches will improve common case access time, not worst case. Tying frequency to worst case path violates first law of performance!! — “Make the common case fast” (we’ll revisit this often) 04 March 2021 Multicycle datapath 38

Summary Performance is one of the most important criteria in judging systems. — Here we’ll focus on Execution time. Our main performance equation explains how performance depends on several factors related to both hardware and software. CPU time. X, P = Instructions executed. P * CPIX, P * Clock cycle time. X It can be hard to measure these factors in real life, but this is a useful guide for comparing systems and designs. A single-cycle CPU has two main disadvantages. — The cycle time is limited by the worst case latency. — It isn’t efficiently using its hardware. Next time, we’ll see how this can be rectified with pipelining. 04 March 2021 Multicycle datapath 39