A Simple Processor Prof Sirer CS 316 Cornell

A Simple Processor Prof. Sirer CS 316 Cornell University

Instructions for(i = 0; I < 10; ++i) printf(“go cornell cs”); Programs are written in a highlevel language li r 2, 10 li r 1, 0 slt r 3, r 1, r 2 bne … 01001001000001010 0100100000000 100010010 C, Java, Python, Miranda, … Loops, control flow, variables Need translation to a lower-level computer understandable format Processors operate on machine language Assembler is human-readable machine language

Basic Computer System A processor executes instructions Processor has some internal state in storage elements (registers) A memory holds instructions and data Harvard architecture: separate insts and data von Neumann architecture: combined inst and data A bus connects the two regs processor bus addr, data, r/w 01010000 10010100 … memory

Instruction Usage Instructions are stored in memory, encoded in binary A basic processor fetches decodes executes one instruction at a time 01001001000001010 0100100000000 100010010 addr data pc cur inst adder decode regs execute

Instruction Types Arithmetic add, subtract, shift left, shift right, multiply, divide compare Control flow unconditional jumps (branches) subroutine call and return Memory load value from memory to a register store value to memory from a register Many other instructions are possible vector add/sub/mul/div, string operations, store internal state of processor, restore internal state of processor, manipulate coprocessor

Instruction Set Architecture The types of operations permissable in machine language define the ISA MIPS: load/store, arithmetic, control flow, … VAX: load/store, arithmetic, control flow, strings, … Cray: vector operations, … Two classes of ISAs Reduced Instruction Set Computers (RISC) Complex Instruction Set Computers (CISC) We’ll study the MIPS ISA in this course

Register file The MIPS register file W 32 clk A r 1 r 2 … r 31 5 32 32 32 -bit registers register 0 is permanently wired to 0 B 32 5 5 WE RWRA RB Write-Enable and RW determine which reg to modify Two output ports A and B RA and RB choose values read on outputs A and B Reads are combinatorial Writes occur on falling edge if WE is high

Memory 32 -bit address data in data out memory 32 -bit data word = 32 bits 2 -bit memory control input 32 2 addr mc 00: read 01: write byte 10: write halfword 11: write word

Instruction Fetch inst memory 32 2 00 pc new pc calculation Read instruction from memory Calculate address of next instruction Fetch next instruction

Arithmetic Instructions op 6 bits rs 5 bits rt rd shamt func 5 bits if op == 0 && func == 0 x 21 R[rd] = R[rs] + R[rt] if op == 0 && func == 0 x 23 R[rd] = R[rs] - R[rt] if op == 0 && func == 0 x 25 R[rd] = R[rs] | R[rt] 6 bits

Arithmetic Ops inst memory 32 register file 2 5 5 5 00 pc new pc calculation control alu

Arithmetic Logic Unit A + cin B Implements add, sub, or, and, shift-left, … Operates on operands in parallel Control mux selects desired output

Arithmetic Ops inst memory 32 register file 2 5 5 5 00 pc new pc calculation control alu

Summary With an ALU and fetch-decode unit, we have the equivalent of Babbage’s computation engine Much faster, more reliable, no mechanical parts Next time: control flow and memory operations