A ScanIsland Based Design Enabling PreBond Testability in
A Scan-Island Based Design Enabling Pre-Bond Testability in Die-Stacked Microprocessors Dean L. Lewis Hsien-Hsin S. Lee Georgia Institute of Technology MARS
Outline Introduction to 3 D Motivation Challenges Design Experimental Results Conclusion Lewis and Lee, Enabling Pre-Bond Testability in 3 D ICs (ITC’ 07) 2
3 D Integration • Technology – Stack multiple active layers vertically – Tightly integrate with die to die (d 2 d) vias • Benefits – Routing freedom – Higher performance – Lower power Kiran Puttaswamy, “Designing High-Performance Microprocessors in 3 -Dimensional Integration Technology, ” Ph. D. dissertation, Georgia Institute of Technology, Atlanta, GA, USA, 2007 Lewis and Lee, Enabling Pre-Bond Testability in 3 D ICs (ITC’ 07) 3
3 D Die Stacking Bond Pads Layer 4 Layer 3 Face to Back Layer 2 Face to Face Layer 1 Lewis and Lee, Enabling Pre-Bond Testability in 3 D ICs (ITC’ 07) 4
3 D Assembly Wafer to Die to Die Lewis and Lee, Enabling Pre-Bond Testability in 3 D ICs (ITC’ 07) 5
3 D Integration and Testability Analog Technology Level DRAM CMOS ALU 4 Architecture Level ALU 3 ALU 2 ALU 1 Bit. Line 2 Bit. Line 1 Bit. Line 0 Lewis and Lee, Enabling Pre-Bond Testability in 3 D ICs (ITC’ 07) Circuits Level 6
95% 100% Motivation 95% 90% Stack Yield 81% 66% 44% 0% 100% Single Layer Yield Lewis and Lee, Enabling Pre-Bond Testability in 3 D ICs (ITC’ 07) 80% 7
Purpose Enable Pre-bond 3 D Test Strategy Hardware Requirements Secondary Concerns Lewis and Lee, Enabling Pre-Bond Testability in 3 D ICs (ITC’ 07) 8
Pre-bond Challenges 9/27
Pre-bond Test Challenges Incomplete Circuits Circuit Level Architectural Level Fetch I Cache Decode Issue Reorder Buffer Commit 10, 000 + Out of Order Execution D Cache Complete Possible Architectural Pre-bond Partition Design Lewis and Lee, Enabling Pre-Bond Testability in 3 D ICs (ITC’ 07) Complete Pre-bond Register Circuit File Design 10
Pre-bond Test Challenges Wafer Probing Probe Pads Lewis and Lee, Enabling Pre-Bond Testability in 3 D ICs (ITC’ 07) 11
Pre-bond Test Challenges Supporting Nets Power, Ground, Clocks, Etc. Complete. Clock. Tree. Nets Net Pre-bond Lewis and Lee, Enabling Pre-Bond Testability in 3 D ICs (ITC’ 07) 12
Proposed Solution 13/27
Test Strategy Alpha 21364 IEEE 1149. 1 TAP CSC ISP 3 D Pre-bond Test LTC CSC IEEE 1149. 1 TAP LTC Lewis and Lee, Enabling Pre-Bond Testability in 3 D ICs (ITC’ 07) 14
Layer Border Scan Flops Bus From Another Layer Post-bond Pre-bond Bus To Another Layer Test_Enable So Low Add Lewis and Lee, Enabling Pre-Bond Testability in 3 D ICs (ITC’ 07) Pipeline Stage Register Scan Registers Si High Add Flags 15
Scan Flops Not Required Post-bond Pre-bond Bus From Another Layer Bus To Another Layer So Low Add Pipeline Stage Register Si Lewis and Lee, Enabling Pre-Bond Testability in 3 D ICs (ITC’ 07) High Add Flags 16
Test Pads Faceside Test Lewis and Lee, Enabling Pre-Bond Testability in 3 D ICs (ITC’ 07) Reuse Post-Bond 17
Power and Ground Planar Die Lewis and Lee, Enabling Pre-Bond Testability in 3 D ICs (ITC’ 07) Die Stack 18
Clock Routing Layer 1 Layer 2 Pre-bond Test Optimized Layer 2 Power/Routing Optimized Lewis and Lee, Enabling Pre-Bond Testability in 3 D ICs (ITC’ 07) 19
Real Clock Tree Lewis and Lee, Enabling Pre-Bond Testability in 3 D ICs (ITC’ 07) 20
Lewis and Lee, Enabling Pre-Bond Testability in 3 D ICs (ITC’ 07) Layer 1 Layer 2 Layer 3 Layer 4 Real 3 D Clock Tree 21
Layer 2 Layer 1 Testable 3 D Clock Tree EN CLK Lewis and Lee, Enabling Pre-Bond Testability in 3 D ICs (ITC’ 07) Layer 4 Layer 3 EN 22
More Trees Are Better Pre-bond Test Reliability X Lewis and Lee, Enabling Pre-Bond Testability in 3 D ICs (ITC’ 07) 23
Experiment and Results 24/27
Experiment • Based on 21264 Architecture • Floorplanned microarchitecture blocks – Two die layers • Determined widths of inter-die buses • Laid out scan cell E. Wong and S. -K. Lim. “ 3 D Floorplanning with Thermal Vias. ” In Design, Automation, and Test in Europe Proceedings, pp. 878 -883, 2006. Lewis and Lee, Enabling Pre-Bond Testability in 3 D ICs (ITC’ 07) 25
Results ICache Int. Q FP EU 1 IE IE U 2 U 4 Layer 1 DCache DTLB 75. 8 μm 2 Inter-die Vias 2397 Scan Cell Count Lewis and Lee, Enabling Pre-Bond Testability in 3 D ICs (ITC’ 07) BPred IE FP FPEU 2 U 1 Map FPQ DIS IRF FP IMap 1 RF Ftch IRF 2 IE U 3 Dcd LSQ Mem Ctlr BIU ITLB Layer 2 Scan Cell Size Two cells per via 4794 Area 0. 363 mm 2 Overhead 0. 165% 26
Conclusion • Pre-bond test a necessity for integrating 10+ layers • Pre-bond test can be achieved with current manufacturing technologies and test techniques Lewis and Lee, Enabling Pre-Bond Testability in 3 D ICs (ITC’ 07) • Area cost is insignificant • Clock can be designed to both enable pre-bond test and maximize power savings 27
Backup Slides 28/27
Scan and Non-Neighboring Blocks Si I Fetch ALU So Lewis and Lee, Enabling Pre-Bond Testability in 3 D ICs (ITC’ 07) 29
Clock Routing Area 2 D Clock 3 D Clock Equal Wiring Required Lewis and Lee, Enabling Pre-Bond Testability in 3 D ICs (ITC’ 07) 30
Clock Routing Area 2 D Clock 3 D Clock 50% More Wire in the Limit Lewis and Lee, Enabling Pre-Bond Testability in 3 D ICs (ITC’ 07) 31
Clock Routing Layer 2 D Clock Lewis and Lee, Enabling Pre-Bond Testability in 3 D ICs (ITC’ 07) 3 D Clock 32
Die-to-Die Bonding Tezzaron Super-Via™ Standard Planar Die Top Layer Metal Device and Metal Layers Bulk Silicon S. Gupta, M. Hilbert, S. Hong, and R. Patti. “Techniques for Producing 3 D ICs with High-Density Interconnect. ” In Proceedings of the 21 st International VLSI Multilevel Interconnection Conference, Waikoloa Beach, HI, USA, 2004 Lewis and Lee, Enabling Pre-Bond Testability in 3 D ICs (ITC’ 07) 33
Die-to-Die Bonding Tezzaron Super-Via™ 1 – Dialectric Fill Lewis and Lee, Enabling Pre-Bond Testability in 3 D ICs (ITC’ 07) 34
Die-to-Die Bonding Tezzaron Super-Via™ 2 – Super-Via™ Etch Lewis and Lee, Enabling Pre-Bond Testability in 3 D ICs (ITC’ 07) 35
Die-to-Die Bonding Tezzaron Super-Via™ 3 – Barrier Deposition Lewis and Lee, Enabling Pre-Bond Testability in 3 D ICs (ITC’ 07) 36
Die-to-Die Bonding Tezzaron Super-Via™ 4 – Connection Etching Lewis and Lee, Enabling Pre-Bond Testability in 3 D ICs (ITC’ 07) 37
Die-to-Die Bonding Tezzaron Super-Via™ 5 – Barrier and Cu Deposition Lewis and Lee, Enabling Pre-Bond Testability in 3 D ICs (ITC’ 07) 38
Die-to-Die Bonding Tezzaron Super-Via™ 6 – Expose Bond Lewis and Lee, Enabling Pre-Bond Testability in 3 D ICs (ITC’ 07) 39
Die-to-Die Bonding Tezzaron Super-Via™ 7 – Bond to Second Layer Thermal Diffusion Bonding Lewis and Lee, Enabling Pre-Bond Testability in 3 D ICs (ITC’ 07) 40
Die-to-Die Bonding Tezzaron Super-Via™ 8 – Thin Second Layer Grinding and CMP Lewis and Lee, Enabling Pre-Bond Testability in 3 D ICs (ITC’ 07) 41
Die-to-Die Bonding Tezzaron Super-Via™ 9 – Expose Via Lewis and Lee, Enabling Pre-Bond Testability in 3 D ICs (ITC’ 07) 42
Die-to-Die Bonding Tezzaron Super-Via™ 10 – Repeat Pad Construction Lewis and Lee, Enabling Pre-Bond Testability in 3 D ICs (ITC’ 07) 43
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