A Robust Fast Pulsed Flip Flop Design By

A Robust, Fast Pulsed Flip. Flop Design By: Arunprasad Venkatraman Rajesh Garg Sunil Khatri Department of Electrical and Computer Engineering, Texas A and M University, College Station, TX

Introduction • High speed VLSI design uses heavy pipelining – Results in increased number of Flip-Flops • For mobile devices – Power consumption is the prime concern – Requires low power Flip-Flops – Also demand for high speed operation • Hence there is a strong need for Flip Flops with: – – High speed Low power Low area Tolerance to PVT variations

Figure of Merit - Timing • Time period T ≥ Tcq + Tsu + d where d – delay of the combinational circuit Tsu – setup time of the Flip-Flop Tcq – clock to Q delay of the Flip-Flop • So Tcq + Tsu is the required figure of merit of the FF, since d is circuit-dependent

Traditional Flip-Flops • Data needs to arrive before the clock edge – So setup time Tsu is positive • Hence Tcq + Tsu is much higher • Want to design a flip-flop with a goal of minimizing the figure of merit Tcq + Tsu • We explored different circuit designs with this goal in mind, while ensuring that the resulting flip-flop achieves – Low power and area – High speed – Robustness to PVT variations

Pulsed Flip-Flops (P-FF) • Broadly: consists of a pulse generator + latch • Pulse is derived from clock edge – So pulse is generated after clock edge Data D Q Latch Clk Pulse Clk Generator Clk Pulse Data • Hence data can arrive even after the clock edge (therefore Tsu may be negative)

Proposed Pulsed Flip-Flop The proposed pulse generator design The latch structure

Operation of Pulse Generator • • Clock falls, node Z is pulled up to VDD Clock rises, N 2 discharges internal node W Until W discharges, N 2 and N 1 helps to discharge Z Very fast slew rates for falling edge of Z Waveforms obtained at various nodes

Experimental Setup • Implemented our Pulse Flip-Flop in BPTM 100 nm • Compared with other Flip-Flop designs – Explicit Flip-Flop – Improved hybrid pulsed Flip-Flop – Traditional D Flip-Flop • Performed Monte Carlo simulations for supply voltage (VDD), channel length (L), threshold voltage (VTH ) variations – 500 Monte Carlo simulations – 3σ = 10% for VDD, L and VTH

Pulsed Flip-Flops Compared Explicit Pulsed Flip-Flop Improved Hybrid latch Flip-Flop

Experimental Results Tcq (ps) FLIPFLOPS Power (µW) Tsu (ps) Thold (ps) Tcq + Tsu (ps) Clock Load (µm 2) µ σ µ s µ σ µ σ OUR PULSED FF 95. 2 8. 5 8. 7 1. 1 -68. 8 11. 2 87. 4 11. 2 26. 3 2. 7 0. 11 HYBRID LATCH PULSED FF 117 14. 7 8. 4 0. 9 -34. 4 1. 9 42 4. 8 82. 6 11. 8 0. 13 EXPLICIT PULSED FF 120. 4 29. 3 14. 6 1. 8 -54. 2 4. 5 108. 2 11. 6 65. 8 7. 3 0. 05 Traditional D-FF 69. 9 1. 5 7. 6 1. 3 21. 4 2. 5 29. 9 3. 1 91. 2 8. 7 0. 09

Layout Comparison Proposed Pulsed Flip-Flop Master-Slave D Flip-Flop • Our proposed pulsed Flip-Flop has 27% lesser area than a traditional D Flip-Flop

Conclusions • We proposed a novel pulsed Flip-Flop (P-FF) design • The performance of our P-FF design is better than other FFs – 60% better Tcq + Tsu than other pulsed Flip-Flops – 40% lower power dissipation than explicit pulsed Flip-Flop – 27% lesser area than a master-slave D Flip-Flop • Our P-FF is more robust to process and voltage variations than other designs considered • • Performed Monte Carlo simulations with varying VDD, L and VTH Our design has the lowest standard deviation of Tcq + Tsu • We can further reduce area and power by sharing pulse generator circuit between several latches