A Review of Processor Design Flow 1022020 coursecpeg

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A Review of Processor Design Flow 10/2/2020 coursecpeg 323 -08 FTopics 1 b. ppt

A Review of Processor Design Flow 10/2/2020 coursecpeg 323 -08 FTopics 1 b. ppt 1

How to design a CPU ? • Instruction-set architecture (ISA) design • Function-level (RTL)

How to design a CPU ? • Instruction-set architecture (ISA) design • Function-level (RTL) design • Component-level design • Gate-level/switch-level design • Circuit-level design 10/2/2020 coursecpeg 323 -08 FTopics 1 b. ppt 2

Design Method Gate Level/circuit level: toward full CAD Register Level: CAD + heuristics/intuition ISA

Design Method Gate Level/circuit level: toward full CAD Register Level: CAD + heuristics/intuition ISA Level: 10/2/2020 mainly heuristic process with simulation validation coursecpeg 323 -08 FTopics 1 b. ppt 3

Arch. /Compiler Design Toolset ISA Simulator System Level Simulator Instruction Set Architecture Design (Microarchitecture

Arch. /Compiler Design Toolset ISA Simulator System Level Simulator Instruction Set Architecture Design (Microarchitecture Design-I) Compiler Design Code Optimizer Code Generator System-Level Design Hardware Design RTL Level Design (Microarchitecture Design II) RTL Level Simulator Switch Level Simulator Processor Architecture Design Flow Diagram Switch Level Design Circuit Level Simulator Circuit Level design HDL (VHDL or Verilog) 10/2/2020 coursecpeg 323 -08 FTopics 1 b. ppt 4

Design Levels of Abstraction Abstract Architecture mov eax, [edi] cmp eax, 4 jne label

Design Levels of Abstraction Abstract Architecture mov eax, [edi] cmp eax, 4 jne label 10 eax ebx ecx C P U edx Logic I-Cache D-Cache Branch Unit Switch Instruction Decode Register Mapping Int Regs Ren. Ifs. Set. Wb 2 H : = v. OR 3(Ren. Cover. Updt. IFMWb 2 H, v. AND 2(Ren. Crab_Data_Hi_Cx 5 B[31], Ren. Crab. Ifs. Wr. En. Cx 5 H), v. AND 2(Ren. Ifs. Valid. Wb 3 H, v. NOT(Ren. Crab. Ifs. Wr. En. Cx 5 H))) Address Calculation FP Regs ALU M I C R O A R C H FPU LAYOUT C I R C U I T 10/2/2020 coursecpeg 323 -08 FTopics 1 b. ppt Concrete 5

Design Levels and Component Types 10/2/2020 coursecpeg 323 -08 FTopics 1 b. ppt 6

Design Levels and Component Types 10/2/2020 coursecpeg 323 -08 FTopics 1 b. ppt 6

Classical ISA Level Design Method • Select a prototype structure A • Modify A

Classical ISA Level Design Method • Select a prototype structure A • Modify A to accommodate: - new performance demand new technology • Evaluation (ISA simulation) • Repeating until satisfaction 10/2/2020 coursecpeg 323 -08 FTopics 1 b. ppt 7

Overall Simulation Strategy 1. Instruction level simulator: this is used for performance evaluation at

Overall Simulation Strategy 1. Instruction level simulator: this is used for performance evaluation at the instruction set level as well as for more detailed modeling, e. g. the pipeline and memory system. This level is also used to generate test vectors employed in lower-level simulators. 2. System level simulation: this simulator models the details of the system environment including such things as interrupts and memory management. (Virtual machine level. . ) 10/2/2020 coursecpeg 323 -08 FTopics 1 b. ppt 8

Overall Simulation Strategy (Con’d) 3. RTL level: this simulator models are RTL description of

Overall Simulation Strategy (Con’d) 3. RTL level: this simulator models are RTL description of the design 4. Switch level with delays: used to simulate the design mostly in components; test vectors are generated from the RTL level. 5. Circuit simulation: it is used for detailed modeling of the critical paths as well as for verification of circuits under variations in temperature, power supply, etc. 10/2/2020 coursecpeg 323 -08 FTopics 1 b. ppt 9

Performance of Simulators # of cycles simulated per second on a host machine 10/2/2020

Performance of Simulators # of cycles simulated per second on a host machine 10/2/2020 coursecpeg 323 -08 FTopics 1 b. ppt 10

Instruction Set Architecture Simulation Object file Architecture Models Execution -driven simulator Traces (e. g.

Instruction Set Architecture Simulation Object file Architecture Models Execution -driven simulator Traces (e. g. memory accesses branch trace, etc. ) Trace-driven simulator (cache simulator branch prediction simulator, etc. ) 10/2/2020 coursecpeg 323 -08 FTopics 1 b. ppt Runtime statistics (frequencies, cycle counts, etc. ) Profile information Statistics (e. g. cache behavior, branch behavior, etc. ) 11

Performance Study by Simulation • Develop performance model that is: Flexible - Parameterized (via

Performance Study by Simulation • Develop performance model that is: Flexible - Parameterized (via knobs) - 95% clock accurate compared to RTL - Significantly smaller than RTL • Models consist of two parts: - Instruction-set simulator -> executes benchmark - Pipeline simulator -> “accountant” for clock cycles • Run benchmarks, update microarchitecture accordingly • Cycle of: code -> simulate -> characterize -> tune - 10/2/2020 coursecpeg 323 -08 FTopics 1 b. ppt 12

Revisit: How to design a CPU ? • Instruction-set architecture (ISA) design • Function-level

Revisit: How to design a CPU ? • Instruction-set architecture (ISA) design • Function-level (RTL) design • Component-level design • Gate-level/switch-level design • Circuit-level design Monty Denneau: I work on everything down to and including 4. Cyclops skips (2) and goes directly to 3/4. A lot of time was spent restructuring the design to make 4 meet timing. I probably spent thousands of hours on 4. We have no 5 - ASICS provides a library of gates, latches, and memory, etc. August 28, 2007 10/2/2020 coursecpeg 323 -08 FTopics 1 b. ppt 13

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