A Random Access Scan Architecture to Reduce Hardware

A Random Access Scan Architecture to Reduce Hardware Overhead Anand S. Mudlapur Vishwani D. Agrawal Adit D. Singh Department of Electrical and Computer Engineering Auburn University, AL 36849 USA 1

Motivation for This Work • Serial scan (SS) test sequence lengths and power consumption are increasing rapidly. – Reduction of test power and test time are complimentary objectives in serial scan. • Scope of increasing delay fault coverage is limited in serial scan. • In spite of the three advantages (test time, power, and delay fault coverage) random access scan (RAS) is not popular due to high overhead. 2

Outline • Introduction • Review of our “toggle” Flip-Flop design • Highlight the uniqueness and feasibility of our design due to the reduction of two global signals • A new scan-out structure • Results on ISCAS Benchmark Circuits • Conclusion 3

Introduction • Random Access Scan (RAS) offers a single solution to the problems faced by serial scan (SS): – Each RAS cell is uniquely addressable for read and write. – RAS reduces test application time and test power which are otherwise complimentary objectives. • Previous and current publications on RAS: • • • Ando, COMPCON-80 Wagner, COMPCON-83 Ito, DAC-90 Baik et al. , VLSI Design-04, ITC-05, ATS-05, VLSI Design-06 Mudlapur et al. , VDAT-05 • Disadvantage: High routing overhead – test control, address and scan-in signals must be routed to all flipflops. 4

Contributions of Present Work • Eliminate scan-in signal from circuit by using a toggling RAS flip-flop. • Eliminate routing of test control signal to flip-flops. • Provide a new scan-out architecture: – A hierarchical scan-out bus – An option of multi-cycle scan-out 5

Serial Scan (SS) PI Combinational Circuit Scan-in FF FF FF PO Scan-out Test control (TC) Example: A circuit with 5, 000 FFs and 10, 000 combinational test vectors Total test cycles = 5, 000 x 10, 000 + 5, 000 = 50, 015, 000 6

Random Access Scan (RAS) PI Address Inputs Combinational Circuit FF FF FF PO Scan-out bus Decoder These signals are eliminated in our design TC During every test, only a subset of all Flip-flops needs to be set and observed for targeted faults Scan-in 7

The “Toggle” RAS Flip-Flop Combinational Logic Data 1 M U 0 X Combinational Logic Data M To Output BUS S Clock x y RAS-FF √nff Lines Row Decoder Address (log 2 nff) Output BUS Control √nff Lines Column Decoder 8

Toggle Flip-Flop Operation Function Clock Normal Data Toggle Data Hold Data Address decoder outputs Row (x) Column (y) Active 0 0 Inactive 1 Active Clock Inactive Active Clock 1 Inactive 1 0 Inactive 0 1 Inactive 0 0 9

Toggle Flip-Flop Operation (contd. ) Unaddressed FFs x 4 Decoded address lines RAS FF 0 y 1 RAS FF 1 y 2 Addressed FF RAS FF 01 y 3 10

Macro Level Idea of Signals to RAS-FF RAS FF 11 RAS FF 12 RAS FF 13 RAS FF 14 RAS FF 21 RAS FF 22 RAS FF 23 RAS FF 24 RAS FF 31 RAS FF 32 RAS FF 33 RAS FF 34 RAS FF 41 RAS FF 42 RAS FF 43 RAS FF 44 4 -to-1 Scan-out Macrocell x 1 x 2 x 3 x 4 y 1 y 2 y 3 y 4 To Next Level 11

Scan-out Macrocell • A 4 x 4 block scan-out data flow and control logic Data Bus From 4 RAS FFs To Next Level Output BUS { • D-FFs may be inserted at the two outputs of Control From 4 RAS FFs Control Signal to Next Level BUS macrocell for multi-cycle scan-out. 12

Routing of Decoder Signals in RAS Address (log 2 √ nff) R O W Flip-Flops Placed on a Grid Structure D E C O D E R COLUMN DECODER 13

Gate Area Overhead Gate area overhead of = Serial Scan Gate area overhead of Random Access Scan = where nff – Number of Flip-Flops ng – Number of Gates Assumption: D-FF contains 10 logic gates. 14

Gate Area Overhead (Examples) 1. A circuit with 100, 000 gates and 5, 000 FFs Gate overhead of serial scan = 13. 3 % Gate overhead of RAS = 20. 0 % (Typical example from an industrial circuit. Details in later slide) 2. A circuit with 500, 000 gates and 5, 000 FFs Gate overhead of serial scan = 3. 6 % Gate overhead of RAS = 5. 5 % 15

Overhead in Terms of Transistors Transistor overhead of = Serial Scan Transistor overhead of = Random Access Scan Where nt is number of transistors in comb. logic. D-flip-flop (28 transistors), serial scan FF (28+10) and RAS FF (28+26) were designed in 0. 5μ CMOS technology using Mentor Graphics Design Architect. 16

Test Time 17

Test Power 18

Case Study on an Industrial Circuit • • A case study on an industry circuit was performed at Texas Instruments India Pvt. Ltd. The preliminary results were as follows: 1. The gate area overhead of RAS for a chip with ~5500 Flip-Flops and ~100, 000 NAND equivalent gates was of the order of 18%. 2. 4 X reduction in test time was estimated. A speed-up of up to 10 X was considered possible using ATPG heuristics. 3. Estimated routing and device area overhead of RAS in physical layout was 10. 4%. 19

Conclusion • New design of a “Toggle” Flip-Flop reduces the RAS routing overhead. • Proposed RAS architecture with new FF has several other advantages: – Algorithmic minimization reduces test cycles by 60%. – Power dissipation during test is reduced by 99%. • A novel RAS scan-out method presented. • For details on “Toggle” Flip-Flop, see Mudlapur et al. , VDAT-05. 20