A new Interlock Design for the TESLA RF

A new Interlock Design for the TESLA RF System H. Leich 1, A. Kretzschmann 1, S. Choroba 2, T. Grevsmühl 2, N. Heidbrook 2, J. Kahl 2, 1(DESY Zeuthen) 2(DESY Hamburg) • The Problem • The Interlock Architecture • Implementation • Status of the Project Holger Leich, DESY Zeuthen

Main Task of the Interlock Sytem --> to prevent any damage from the cost expensive components of the RF station --> also to prevent any damage from other environment Sources of Interlock Error Signals • hard component failures (non-reversible hardware malfunction) --> broken cable or damaged contact, dead sensor, . . . • soft errors (e. g. sparks in the klystron or wave guide system, temperature above a threshold, . . . ) • error conditions caused by transient noise from the RF station itself Holger Leich, DESY Zeuthen

PITZ Interlock Subsystems Control system Clear, Clock, Dout Din Klystron interlock safety & person IL o. k. RF- leak 1&2 enable Klystron 1&2 12 gun signals separate Clock. . . Low level RF all input signals internal states output signals masks to BIS all input signals internal states output signals enable magnets 1 & 2 laser pulse length laser rep. Rate enable RF enable alig. laser Gun IL o. k. reset gun interlock laser shutter Magnets Beam inhibit system PM Gun fast 9 analog signals ADCs enable BIS 1&2 enable shutter 1 1&2 enable RF Laser interlock Person interlock Gun interlock Holger Leich, DESY Zeuthen Profibus solenoid supply o. k.

Architecture of the existing Interlock Strictly digital hierarchical Interlock Process Analysis Output to Process Analog Process Input Digital Process Input Sensor Analog Output Adapter Unit Klystron, RF Station Holger Leich, DESY Zeuthen Digital Output Adapter Unit

Klystron Interlock Inputs • Digital Inputs - Oil levels - Cooling water flow - Vacuum pump current • Analog Inputs - Oil temperature - Cooling water temperature - Heater current - Solenoid current - SF 6 gas pressure Holger Leich, DESY Zeuthen

Klystron Interlock Inputs / Outputs • Preprocessed Inputs - Person interlock o. k - RF leakage detector - Modulator ready - Gun interlock o. k. - RF system ready • Interlock Outputs - Modulator on - Heater power supply on - Solenoid power supply on - RF enable Holger Leich, DESY Zeuthen

Response Times • Ultra Fast (UF): Rt < 1 µs • Fast (F): Rt = 1. . . 5 µs • Slow (SL): Rt > 5 µs --> Actual implementation only SL and F --> ca. 40 signals to process Holger Leich, DESY Zeuthen

Overview over the new Interlock Design Master Control System Component Characteristics Predefined Curve Data Measured Characteristic Interlock Logic implemented based on a Microcontroller (Processor Core) User programmable ASIC (FPGA) Time discrete digital data Analog Process Input Digital Process Input Sensor Analog/Digital Process Output Adapter Unit Klystron, RF Station Holger Leich, DESY Zeuthen

The Implementation Constraints limited space in TESLA-tunnel • combine Control & Interlock Functions into only one crate per RF-station • perform communication between modules via backplane ( no extra cable for communication) • process-I/O with no cables to the front side of the crate; all cables from rear site Other, DESY defined constraints • use a standard with stable, fast enough & easy to implement bus interface • use a standard that gives flexibility at the level of system integration ( definition of backplane-ressources : standard bus, user defined bus, …) • use a standard that saves investment over longer time scale • use a standard to have the option to buy commercial available products (CPU`s, DAQ components, piggy pack, e. g. IP modules, . . . ) • use a standard that offers the option of additional boardspace (rear transition option) Holger Leich, DESY Zeuthen

Implementation Details DESY decision: Use a VME 64 x system - VME 64 x introduces 5 row (160 pins) connectors J 1/J 2 and an optional 95 pin-connector J 0 415 pins Total = 210 pins VME System + 205 pins User Defined => enough pin resources per slot and per backplane to build a compact interlock/control system • VME is a stable, fast enough and easy to implement bus and instrumentation system • mixed use of VME and VME 64 x devices possible • rear transition board option • easy system integration DESY: 205 pins User Defined: 64 pins per slot used for rear transition 141 pins across the backplane to implement a fast user bus Holger Leich, DESY Zeuthen

DESY-VME 64 x-Backplane ( slot-pin configuration ) 1 z a b c d 32 1 e d c b a z a b c d J 1 J 0 19 1 J 2 per Slot 32 141 pin User Defined Bus (GTL) Rear I/O Connections: 64 pins Holger Leich, DESY Zeuthen VME 64 x Standard

VME-CPU (VME-Controller) HD Profibus Reserve Interlock Master / Sequencer Interlock / Control Crate Up to 16 I/O-Modules Control- / Monitoring Interlock Holger Leich, DESY Zeuthen

Interlock / Control Crate (Side view) Front Boards (160 mm) Rear Boards (160 mm) J 1 VMEbus Interface • Additional I/O-functions Interlock / Master Logic I/O resources • Rear Transition Signals J 0 • Signal conditioning User Bus Interface J 2 VME 64 x Backplane, 160 pin-J 1/J 2, 95 pin-J 0 (with J 0 full & J 2 -pins rows z, d bussed) Holger Leich, DESY Zeuthen

Structure of the DESY User Defined Bus Sytem Master / Sequencer 110 lines connected: 22 Time-Mux-Bus 34 Control-Bus 16 Event-Bus 2 Bus. Init, Bus. Clock 4 Reserve Bus. Control 32 Reserve (bi-directional) Bus. Init, Bus. Clock Time-Multiplex-Bus Control-Bus Event-Bus I/O-Module & other Modules Reserve (all lines GTL) 31 lines spare at backplane for free use by other (future) components / systems Event-Bus and/or Reserve could be defined as “LAM” (Emergency Line) for Interlock Signals with very high priority Holger Leich, DESY Zeuthen

Bus Timing • Time Mux Bus BCLK Init_l ADDR Data D(0) 3 2 1 0 D(1) D(2) D(3) • Control Bus BCLK STRB_l WE_l Address ADDRi Data Out Data ADDRj Data In • Event Bus BCLK SRVRQ_l Holger Leich, DESY Zeuthen

Architecture of the Interlock Master / Sequencer ACEX EP 1 K 100 FC 484 VME Access Control VME Interrupt Control Req Ack Ctrl Out Req Ack Req Interlock I/O Boards Dtack, Berr, IRQ[7. . 4], Iack. Out Ack `F 38 ROM Access Arbiter & Address Mux `ABT 162244 Ctrl In Interlock Logic (Sequencer/ Controller) AM[5. . 0], AS, DS[1. . 0], Write, LWord, `ABT 2244 Iack, Iack. In ROM 512 x 16 DPM Access Control Data Out Data In Data Mux VME Bus Address Bus A[23. . 1] Ack Req Data Bus DB[15. . 0] Data Bus CS CE WE Address Mux Nonvolatile SRAM 64 K x 16 (4 x U 634 H 256 CSK 25) Holger Leich, DESY Zeuthen Address Bus `ABT 2244

Other Modules under Construction • Digital Input Module • Digital Output normal • Digital Output ultrafast • Analog IO fast • Digital IO LWL (Rear Module) Holger Leich, DESY Zeuthen

Status of the Project • Architecture definition finished • Backplane design & manufacturing finished • Master/Sequencer design finished/assembled/tested • I/O Module design Digi. In: assembled, not yet tested Digi. Out, Digi. Out. Fast: layout process Analog I/O: design not yet finished Digital IO LWL: not yet designed • Firmware design ongoing Holger Leich, DESY Zeuthen

Existing RF Interlock System Holger Leich, DESY Zeuthen

VME 64 x-Crate with DESY VME 64 x Backplane Holger Leich, DESY Zeuthen

Interlock Master / Sequencer Module Holger Leich, DESY Zeuthen