A Lithographyfriendly Structured ASIC Design Approach By Salman

A Lithography-friendly Structured ASIC Design Approach By: Salman Goplani* Rajesh Garg # Sunil P Khatri # Mosong Cheng # *National Instruments, Austin, TX 78759 # Department of ECE, Texas A&M University, College Station, TX 1

Outline n Motivation Mask costs increasing n Systematic process variations increasing n Previous Work n Our Approach n n NAND 2 based circuit implementation methodology Experimental Results n Conclusions n 2

Motivation – Mask Costs Process (microns) 2. 0 0. 8 0. 6 0. 35 0. 25 0. 18 0. 13 0. 1 Single Mask Cost ($K) 1. 5 2. 5 4. 5 7. 5 12 40 60 # of Masks 12 12 12 16 20 26 30 34 Mask Set cost ($K) 18 18 30 72 150 312 1000 2000 n n n A full set of lithography masks can cost between $1 -3 M. Roughly 25% reduction in ASIC design starts in past 7 years. [Sematech Annual Report 2002], [ A. Sangiovanni-Vincentelli “The Tides of EDA”, keynote talk, DAC 2003]. Need an approach in which different designs share a set of masks 3

Motivation - Variations n Process variations can be classified as n n n Random variations are unpredictable n n Random variations Systematic variations Caused by random fluctuations such as number of dopant atoms Systematic variations n n Predictable variation trends across a chip Caused by spatial dependencies during device processing n n n Chemical and mechanical polishing (CMP) Optical proximity effects (OPE) Changes in poly shapes translates into channel length variations n Impacts circuit performance more severely compared to metal 4

Motivation – Structured ASICs n Standard cell based design approach (ASIC) n n Severely affected by OPEs due to lack of regularity in design Optical proximity correction (OPC) is performed to deal with OPEs n OPC needs to be performed on all layers for each new ASIC design n n Need a circuit design approach that n n n Computationally expensive process Allows us to share a majority of fabrication masks across different designs Allows us to share the OPC computation for some layers, across different designs Our approach achieves these goals 5

Previous Work n Jayakumar et. al. 2004 proposed a structured ASIC approach using a network of fixed (medium) sized PLAs n n Gulati et. al. 2007 reported a pass transistor logic (PTL) based structured ASIC approach n n n Large delay (area) overhead of ~260% (~240%) Delay and area overheads are ~50% and ~240% Pillegi et. al. 2003 reported that FPGAs are typically ~25 X slower than ASICs Our approach provides a structured ASIC solution with small area (~10%) and delay (~35%) overheads 6

Our Solution n Use a regular array of 2 -input NAND cells as the underlying circuit structure, and customize only METAL and VIA masks n n To create an ASIC for a given design – technologymap this design to the smallest available NAND 2 array n n n NAND 2 is functionally complete Stock such arrays pre-processed until metallization step Or, use previously generated masks for all other layers and use new masks for only METAL, VIA layers Only METAL and VIA masks require changes Easier to fix bugs, since only METAL and VIA masks change Optimize poly layer mask for maximum yield n n Perform aggressive OPC on the poly layer Required to be done only once 7

NAND 2 Cell Array n NAND 2 cells are placed to create rectangular array of cells n Some space is left between two rows of NAND 2 cells n Used for routing 8

NAND 2 Cell n n n Size- 1. 6 mm X 2. 6 mm Input/output pins on Metal 1 Symmetrical along vertical axis up to poly layer n n n Placer can map to original or flipped cell orientation, thereby reducing area Poly and diffusion layers unchanged if a cell is flipped, hence same masks used for either orientation. Layout of NAND 2 cell is lithographyfriendly n n n No bends in poly Poly on a fixed pitch (as required in more recent fabrication processes) Good for manufacturability reasons 9

Circuit Mapping to NAND 2 Array n Library L consists of 1 X, 2 X, 3 X and 4 X NAND 2 cells n 2 X, 3 X and 4 X NAND 2 cells are implemented by connecting 2, 3 and 4 NAND 2 cells in parallel Combination circuit N in blif format Technology indep. opt. of N N* Map N* with L for area or delay N 1 Place N 2 using QPLACE -SEDSM and Route using WROUTE N 2 Replace all 2 X, 3 X or 4 X NAND 2 cells in N 1 by 2, 3 or 4 1 X NAND 2 cells 10

Characterization of NAND 2 Array n Delay (D) is obtained using the sense package in SIS n n n Sense reports the largest sensitizeable delay of the circuit (excludes any false paths) We use gate netlist N 1 with 1 X, 2 X, 3 X and 4 X NAND 2 Power - dynamic power of a circuit is n n f (= 1/D) is the operating frequency of circuit Ceff is the total switching capacitance where: Ck is the capacitance of the node k is the probability of transition of the node 11 k

Characterization of NAND 2 Array n Transition probability of the node k is given by where: pk is the probability that node k is at logic “ 1” n Probability pk is obtained using the approach of Gulati et. al. 2005 n n n pk = 0. 5 for primary inputs For any node, obtain pk by propagating input probabilities based on node functionality Area is obtained by placing and routing N 2 using SEDSM tools from Cadence n All benchmark circuits are routed using up to 4 Metal layers 12

Characterization of NAND 2 Array n OPC and lithographical simulations n n n Used Calibre tool from Mentor Graphics We used optical model with l = 193 nm Constant threshold resist model was used We perform OPC on poly and metal layers (referred to as M) of the placed and routed N 2 design. Resulting layers are referred to as MOPC Lithographical simulations are then performed on all layers in MOPC to obtain resulting layers MSIM Error is the area of layer EM which is given by EM = XOR(M, MSIM) 13

Experimental Results n Designed NAND 2 cells library L using 100 BPTM with VDD = 1. 2 V n n n Also implemented standard cell library LSTD L contains 1 X, 2 X, 3 X and 4 X NAND 2 cells LSTD consists of INV and NAND, NOR, AND & OR gates (with 2 and 3 inputs) Implemented several ISCAS and MCNC benchmark circuits using our approach and ASIC approach We mapped these designs for both area and delay optimality 14

Area, Delay and Power n Average results for several circuits implemented using our NAND 2 structured ASIC approach and traditional ASIC approach n Detailed results in paper Performance Parameter Area Mapped Ratio (NAND 2/ASIC) Delay Mapped Ratio (NAND 2/ASIC) Area 1. 08 1. 12 Delay 1. 31 1. 39 Power 0. 91 1. 07 15

Lithography Simulation n n Ratio of lithographical error for poly and Metal 1 -4 layers for both approaches EP EM 1 EM 2 EM 3 EM 4 Area Mapped 0. 93 0. 76 1. 12 1. 00 1. 09 Delay Mapped 0. 94 0. 71 1. 19 1. 05 1. 06 Errors on poly and Metal 1 for our approach is lower than ASIC approach n n Poly error translates into channel length variations Sheet resistivity of Metal 1 is higher than Metal 2 -4 Wires in these layers is largely restricted to within the cell alone Our approach uses more wiring on Metal 2 -4 due to an overall area increase, resulting in an increase in error on these layers 16

Conclusions n With increasing cost of masks and process variations n n We presented a new structured ASIC approach n n Implements circuits using regular array of 2 -input NAND gates Our approach has small overheads compared to standard cell (ASIC) based design approach n n Need to implement circuits using regular structures Area - 12% Delay - 40% Power - 7% Lithographical errors of our approach are lower on poly and Metal 1 layers by 7% and 24% compared to ASIC approach n Our approach is lithography friendly 17

` Thank You!! 18

Backup Slides 19

AREA 20

Delay 21

Power 22

Lithographical Error 23

Implementing Sequential Circuits n Flip Flop can be implemented using NAND 2 gates as shown 24

Circuit Mapping to NAND 2 Array n Library L- 1 X, 2 X, 3 X and 4 X NAND 2 cells n n 2 X, 3 X and 4 X NAND 2 cells are implemented by connecting 2, 3 and 4 NAND 2 cells in parallel Circuit mapping Combination circuit N in blif format Technology Indep. Opt. of N SIS N* N 2 Map N* with L for N 1 Area and Delay Mapped Circuit N 2 using only 1 X NAND 2 Replace all 2 X, 3 X and 4 X NAND 2 cells by 2, 3 and 4 1 X NAND 2 Cells 25