A Greatest Common Divisor GCD Processor Discussion D

Euclid’s GCD algorithm 1: 2: 3: 4: 5: 6: 7: 8: 9: 10: 11:

1: 2: 3: 4: 5: 6: 7: 8: 9: 10: 11: int x, y;

clr clk GCD clr clk Z C PA PB GCD Control Unit r 0

gcdpath. vhd -- Title: GCD Datapath library IEEE; use IEEE. STD_LOGIC_1164. all; use IEEE.

gcdpath. vhd (cont. ) architecture GCDpath_arch of GCDpath is signal y, a, PEs, PCs,

gcdpath. vhd (cont. ) alu 1: alu generic map(width => bus_width) port map (a

gcdpath. vhd (cont. ) W: reg generic map(width => bus_width) port map (d =>

VHDL Mealy Machine process(present_state, x) s(t+1) C 1 x(t) present input next state State

gcd_control. vhd -- Title: GCD Control Unit library IEEE; use IEEE. std_logic_1164. all; use

gcd_control. vhd (cont. ) architecture gcd_control_arch of gcd_control is type state_type is (s 0,

gcd_control. vhd (cont. ) C 1: process(current_state, Z, C) begin case current_state is when

gcd_control. vhd (cont. ) when s 5 => next_state <= s 2; when s

gcd_control. vhd (cont. ) C 2: process(current_state) begin -- Initialize all outputs alusel <=

gcd_control. vhd (cont. ) when s 1 => -- R 1 <- Y r

gcd_control. vhd (cont. ) when s 4 => -- W <- R 0 r

gcd_control. vhd (cont. ) when s 7 => -- W <- R 0 r

GCD. vhd -- Title: Greatest Common Divisor library IEEE; use IEEE. STD_LOGIC_1164. all; use

GCD. vhd (cont. ) architecture GCD_arch of GCD is signal alusel: std_logic_vector(2 downto 0);

begin GCD. vhd (cont. ) U 1: gcdpath generic map(width => width) port map

GCDtest. vhd -- Title: GCD Test library IEEE; use IEEE. STD_LOGIC_1164. all; use IEEE.

GCDtest. vhd (cont. ) architecture GCDtest_arch of GCDtest is signal r, p: std_logic_vector(15 downto

GCDtest. vhd (cont. ) -- Divide the master clock (50 Mhz) process (mclk) begin

GCDtest. vhd (cont. ) U 1: GCD generic map(width => bus_width) port map (PA

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A Greatest Common Divisor (GCD) Processor Discussion D 11. 4

Euclid’s GCD algorithm 1: 2: 3: 4: 5: 6: 7: 8: 9: 10: 11: int x, y; x = x_input; y = y_input; while (x != y) { if (x<y) y = y-x; else x = x-y; } output = x; GCD(9, 15) x=9 y = 15 – 9 = 6 x=9– 6=3 y=6– 3=3 GCD(9, 15) = 3

ALU

1: 2: 3: 4: 5: 6: 7: 8: 9: 10: 11: int x, y; x = x_input; y = y_input; while (x != y) { if (x<y) y = y-x; else x = x-y; } output = x;

clr clk GCD clr clk Z C PA PB GCD Control Unit r 0 ld r 1 ld wld stld msel(1: 0) alusel(2: 0) GCD Datapath PE

gcdpath. vhd -- Title: GCD Datapath library IEEE; use IEEE. STD_LOGIC_1164. all; use IEEE. std_logic_unsigned. all; use work. gcd_components. all; entity GCDpath is generic(width: positive); port( PA: in STD_LOGIC_VECTOR (width-1 downto 0); PB: in STD_LOGIC_VECTOR (width-1 downto 0); alusel: in STD_LOGIC_VECTOR (2 downto 0); msel: in STD_LOGIC_VECTOR (1 downto 0); r 0 ld, r 1 ld, stld, wld: in STD_LOGIC; clr, clk: in STD_LOGIC; C, Z: out STD_LOGIC; PE: out STD_LOGIC_VECTOR (width-1 downto 0) ); end GCDpath;

gcdpath. vhd (cont. ) architecture GCDpath_arch of GCDpath is signal y, a, PEs, PCs, PDs: std_logic_vector(width-1 downto 0); signal s, status: std_logic_vector(3 downto 0); constant bus_width: integer : = 4; constant status_width: integer : = 4; begin a s y

gcdpath. vhd (cont. ) alu 1: alu generic map(width => bus_width) port map (a => a, b => PEs, alusel => alusel, status => s, y => y); R 0: reg generic map(width => bus_width) port map (d => y, load =>r 0 ld, clr => clr, clk =>clk, q => PDs); R 1: reg generic map(width => bus_width) port map (d => y, load => r 1 ld, clr => clr, clk =>clk, q => PCs); stat: reg generic map(width => status_width) port map (d => s, load =>stld, clr => clr, clk =>clk, q => status); a s y

gcdpath. vhd (cont. ) W: reg generic map(width => bus_width) port map (d => y, load => wld, clr => clr, clk =>clk, q => PEs); M 1: mux 4 g generic map(width => bus_width) port map (a => PA, b => PB, c => PCs, d => PDs, sel => msel, y => a); C <= status(0); Z <= status(2); PE <= PEs; end GCDpath_arch; a s y

clr clk GCD clr clk Z C PA PB GCD Control Unit r 0 ld r 1 ld wld stld msel(1: 0) alusel(2: 0) GCD Datapath PE

1: 2: 3: 4: 5: 6: 7: 8: 9: 10: 11: int x, y; x = x_input; y = y_input; while (x != y) { if (x<y) y = y-x; else x = x-y; } output = x;

VHDL Mealy Machine process(present_state, x) s(t+1) C 1 x(t) present input next state State Register init s(t) present state process(present_state, x) clk process(clk, init) z(t) C 2

gcd_control. vhd -- Title: GCD Control Unit library IEEE; use IEEE. std_logic_1164. all; use IEEE. std_logic_unsigned. all; entity gcd_control is port ( clr: in STD_LOGIC; clk: in STD_LOGIC; Z: in STD_LOGIC; C: in STD_LOGIC; alusel: out STD_LOGIC_VECTOR (2 downto 0); msel: out STD_LOGIC_VECTOR (1 downto 0); r 0 ld, r 1 ld, stld, wld: out STD_LOGIC ); end gcd_control;

gcd_control. vhd (cont. ) architecture gcd_control_arch of gcd_control is type state_type is (s 0, s 1, s 2, s 3, s 4, s 5, s 6, s 7); signal current_state, next_state: state_type; begin statereg: process(clk, clr) -- the state register begin if clr = '1' then current_state <= s 0; elsif (clk'event and clk = '1') then current_state <= next_state; end if; end process statereg;

gcd_control. vhd (cont. ) C 1: process(current_state, Z, C) begin case current_state is when s 0 => next_state <= s 1; when s 1 => next_state <= s 2; when s 2 => next_state <= s 3; when s 3 => next_state <= s 4; when s 4 => if Z = '1' then next_state <= s 7; elsif C = '1' then next_state <= s 5; else next_state <= s 6; end if;

gcd_control. vhd (cont. ) when s 5 => next_state <= s 2; when s 6 => next_state <= s 2; when s 7 => next_state <= s 7; end case; end process C 1;

gcd_control. vhd (cont. ) C 2: process(current_state) begin -- Initialize all outputs alusel <= "000"; msel <= "00"; r 0 ld <= '0'; r 1 ld <= '0'; stld <= '0'; wld <= '0'; a s y case current_state is when s 0 => -- R 0 <- x r 0 ld <= '1' ; r 1 ld <= '0'; stld <= '1'; wld <= '0'; msel <= "00"; alusel <= "000";

gcd_control. vhd (cont. ) when s 1 => -- R 1 <- Y r 0 ld <= '0' ; r 1 ld <= '1'; stld <= '1'; wld <= '0'; msel <= "01"; alusel <= "000"; when s 2 => -- W <- R 0 r 0 ld <= '0' ; r 1 ld <= '0'; stld <= '1'; wld <= '1'; msel <= "11"; alusel <= "000"; when s 3 => -- W <- R 1 - W r 0 ld <= '0' ; r 1 ld <= '0'; stld <= '1'; wld <= '1'; msel <= "10"; alusel <= "010"; a s y

gcd_control. vhd (cont. ) when s 4 => -- W <- R 0 r 0 ld <= '0' ; r 1 ld <= '0'; stld <= '1'; wld <= '1'; msel <= "11"; alusel <= "000"; when s 5 => -- R 0 <- W - R 1 r 0 ld <= '1' ; r 1 ld <= '0'; stld <= '1'; wld <= '0'; msel <= "10"; alusel <= "011"; when s 6 => -- R 1 <- R 1 - W r 0 ld <= '0' ; r 1 ld <= '1'; stld <= '1'; wld <= '0'; msel <= "10"; alusel <= "010"; a s y

gcd_control. vhd (cont. ) when s 7 => -- W <- R 0 r 0 ld <= '0' ; r 1 ld <= '0'; stld <= '1'; wld <= '1'; msel <= "11"; alusel <= "000"; when others => null; end case; end process C 2; end gcd_control_arch; a s y

clr clk GCD clr clk Z C PA PB GCD Control Unit r 0 ld r 1 ld wld stld msel(1: 0) alusel(2: 0) GCD Datapath PE

GCD. vhd -- Title: Greatest Common Divisor library IEEE; use IEEE. STD_LOGIC_1164. all; use IEEE. std_logic_unsigned. all; use work. GCD_components. all; entity GCD is generic(width: positive); port( PA: in STD_LOGIC_VECTOR ((width-1) downto 0); PB: in STD_LOGIC_VECTOR ((width-1) downto 0); clr, clk: in STD_LOGIC; PE: out STD_LOGIC_VECTOR ((width-1) downto 0) ); end GCD;

GCD. vhd (cont. ) architecture GCD_arch of GCD is signal alusel: std_logic_vector(2 downto 0); msel: std_logic_vector(1 downto 0); C, Z: std_logic; r 0 ld, r 1 ld, stld, wld: std_logic;

begin GCD. vhd (cont. ) U 1: gcdpath generic map(width => width) port map (PA => PA, PB => PB, alusel => alusel, msel => msel, r 0 ld => r 0 ld, r 1 ld => r 1 ld, stld => stld, wld => wld, clr => clr, clk =>clk, PE => PE, C => C, Z => Z); U 2: gcd_control port map (alusel => alusel, msel => msel, C => C, Z => Z, r 0 ld => r 0 ld, r 1 ld => r 1 ld, stld => stld, wld => wld, clr => clr, clk => clk); end GCD_arch;

GCDtest. vhd -- Title: GCD Test library IEEE; use IEEE. STD_LOGIC_1164. all; use IEEE. std_logic_unsigned. all; use work. GCD_components. all; entity GCDtest is port( mclk SW : BTN: LD : Ato. G AN : ); end GCDtest; : in STD_LOGIC; in STD_LOGIC_VECTOR(7 downto 0); in STD_LOGIC_VECTOR(3 downto 0); out STD_LOGIC_VECTOR(7 downto 0); : out STD_LOGIC_VECTOR(6 downto 0); out STD_LOGIC_VECTOR(3 downto 0)

GCDtest. vhd (cont. ) architecture GCDtest_arch of GCDtest is signal r, p: std_logic_vector(15 downto 0); signal clr, clk, cclk, bnbuf: std_logic; signal clkdiv: std_logic_vector(26 downto 0); constant bus_width: positive : = 4; begin clr <= BTN(3);

GCDtest. vhd (cont. ) -- Divide the master clock (50 Mhz) process (mclk) begin if mclk = '1' and mclk'Event then clkdiv <= clkdiv + 1; end if; end process; clk <= clkdiv(0); cclk <= clkdiv(17); -- 25 MHz -- 190 Hz r(15 downto 4) <= "000000";

GCDtest. vhd (cont. ) U 1: GCD generic map(width => bus_width) port map (PA => SW(7 downto 4), PB =>SW(3 downto 0), clr => clr, clk =>clk, PE => r(3 downto 0)); U 2: binbcd port map (B => r, P => p); U 3: x 7 segb port map (x => p, cclk => cclk, clr => clr, Ato. G => Ato. G, AN => AN); LD <= SW; end GCDtest_arch;

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