A DepthFirstSearch Controlled Gridless Incremental Routing Algorithm for

A Depth-First-Search Controlled Gridless Incremental Routing Algorithm for VLSI Circuits Hasan Arslan and Shantanu Dutt Electrical & Computer Eng. University of Illinois at Chicago ICCD 2004

Outline • Introduction • Importance of Incremental Routing • Previous work • Our Goals • A DFS-Based Incr. Routing Alg. • Non-Uniform Grids • DSR (Depth first search controlled Segment bump and Refit) Algorithm • Experimental Results • Conclusion

Introduction • In current VLSI Chip • The size gets smaller • High clock frequency • Interconnections on chip very important • Technical Problems • • Wire-congestion and routability Crosstalk / noise Power consumption Terminal distribution

Incremental Routing • After a chip layout is completed • Time/noise violation • One or more optimization metrics • Technology constraints • Make changes to the circuit/system • Engineering Change Order (ECO) process • Time to meet market requirements • Enormous resources and time already spent. • Need a time-efficient & effective incremental routing algorithm

Incremental Routing (Cont. ) • Incremental Routing Problem • Set of existing routed nets R • Set of new nets S (due to timing violation, noise…) • Quality metrics for an Incr. Routing • Near-optimal incr. solutions in a short amount of time • Preserve previous routing results as much as possible • Complete the required incremental routing in the available channel area if such a solution exists

Prior work on Incremental Routing • 1) Emmert and Bhatia, “Incremental Routing in FPGA” , IEEE Int. ASIC Conference, 1998. • 2) Cong and Sarrafzadeh, “Incremental Physical Design” , ISPD 2000. • 3) Dutt, Shanmugavel and Trimberger, “Efficient Incremental Rerouting for Fault Reconfiguration in FPGAs”, ICCAD 1999. • 4) Dutt, Verma and Arslan “A Search-Based Bump and Refit Approach to Incremental Routing for ECO Applications in FPGAs”, TODAES 2002 • 5) Xiang, Chao, Wong “An ECO Algorithm for Eliminating Crossalk Violations”, ISPD 2004

Emmert-Bhatia (ASIC’ 98) • • Nets connected to faulty PLB, deleted and rerouted A graph is built, from source pin to target pin Standard single-net routing mode (global then detailed) Do not perturb or move existing nets Cong-Sarrafzadeh (ISPD’ 00) • Single Net Routing : Route new nets without removing any existing nets. • Rip & Reroute : If some nets cannot be routed, rip-up the existing nets which occupy the resources of new nets. Reroute the ripped up nets.

Dutt, Shanmugavel and Trimberger (ICCAD’ 99) • Used incremental rerouting for dynamic fault reconfiguration in FPGAs • Does not rip-up and reroute • Shift them (or their subnets) to other track positions --Bump-&-Refit (B&R) • No change in topology, length of existing nets • Optimal: Finds a detailed route if exists Dutt, Verma and Arslan (TODAES’ 02) • Extended basic B&R significantly for: – full incremental routing (global + detailed) – complex switchboxes – much better results than Std and R&R (routing succ within avail res, HP of failed nets, speed under certain conditions)

Our Goals • Incremental routing for VLSI (ASIC) circuits • Gridless framework for non-uniform width & spacing req. and memory & time efficiency • Address the quality metrics of incr. routing – Near-optimal incr. solutions (min. WL and vias) in a short amt. of time – Preserve previous routing results as much as possible – Complete the required incremental routing in the available channel area if such a solution exists = min. # of metal layers = max. routing success in given layers • Approach: – Allow bumping of existing nets for near-optimal solns to new nets – However, to obtain an overall good solution control the amount of perturbation of existing nets or their routing failures by retracting their bumpings using an overall DFS control

DFS-Based Incr. Routing Alg. (Incr. Routing Concepts) Adjacent-via n 2 n 1 R-BBox n 2 n 1

DFS-Based Incr. Routing Alg. (Incr. Routing Concepts) • If there is an edge between two nets in OG, they might bump each other during shifting one of them. CG of n 1. v 1 ob 1 n 2. h 1 n 1. h 1 n 2. v 1 n 2 n 1. v 1 n 1. h 1 possible overlapping ob 1 n 2. v 1 n 2. h 1 CG of n 2 For net ni in OG • higher degree (more adj. net in OG) might bump more nets, passing through in dense area • Check only adj. nets/blocks in OG to create non-uniform grid for ni

DFS-Based Incr. Routing Alg. Do-DFS-Routing(ni) Route-with-Bumping(ni) Generate grid line in R-BB Cp=Get-Candidate-Paths Route-without-Bumping(ni) All paths in Cp tested? return(succ. ) YES return(fail) Soln? NO Route-with-Bumping(ni) YES For each bumped net nk Do-DFS-Routing(nk) return(succ. ) YES Soln? NO return(fail) Retract curr. bumping-causing routing path

Non-Uniform Grid Extraction • Variable width/spacing rule Width / space req. of new net To route new net • Create obstruction zone around existing nets • Find zero width path for new net

Non-Uniform Grid Extr. & Routing t BGLs (Boundary Grid Lines) VGLs (Vacant Grid Lines) s OGLs (Occupied Grid Lines) • Use VGLs to get solution without bumping. • Use VGLs and OGLs to do B&R type routing (OGLs has higher cost than VGLs).

DFS-Based Incr. Routing Alg. Do-DFS-Routing(ni) Route-with-Bumping(ni) Cp=Get-Candidate-Paths Generate grid line in R-BB Route-without-Bumping(ni) return(succ. ) YES All paths in Cp tested? return(fail) NO Soln? NO Route-with-Bumping(ni) YES Get-Next-Path(CP) For each bumped net nk Do-DFS-Routing(nk) return(succ. ) Soln? NO return(fail) YES Soln? NO Retract curr. bumping-causing Routing path

Finding Solution without Bumping – Use the 4 via Algorithm (Carothers, Lee, T-CS, 1999) 1 -via routing 2 -via routing Adj-via n 1 nj n 2 n 3 n 1 Adj-via Bumped seg. n 2 n 1 Adj-via If 3 -via 1 -via path cannot be found due to obstacles 2 -via 3 -via routing 4 -via routing Adj-via n 1 cv n 1 Adj-via cv

DFS-Based Incr. Routing Alg. Do-DFS-Routing(ni) Route-with-Bumping(ni) Cp=Get-Candidate-Paths Generate grid line in R-BB Route-without-Bumping(ni) return(succ. ) YES All paths of Cp tested? return(fail) NO solution NO Route-with-Bumping(ni) YES Get-Next-Path(Cp) For each bumped net nk Do-DFS-Routing(nk) return(succ. ) Soln? NO return(fail) YES Soln? NO Retract curr. bumping-causing Routing path

Selecting Paths to Route Bumped Seg. Adj-via n 1 n 1 Adj-via Equal distance m paths Random m paths Adj-via n 1 The first m paths The randomized initial path set selection gave the best solutions in terms of both quality and runtime.

DFS-Based Incr. Routing Alg. Do-DFS-Routing(ni) Route-with-Bumping(ni) Cp=Get-Candidate-Paths Generate grid line in R-BB Route-without-Bumping(ni) return(succ. ) YES Have all path of CP tested return(failed) Soln? NO Route-with-Bumping(ni) YES Get-Next-Path(CP) For each bumped net nk Do-DFS-Routing(nk) return(succ. ) Soln? NO return(failed) NO YES solution NO Retract previous bumping-causing routing

DFS-Controlled Routing with Bump & Refit n 3. . v 1 nj n 2 n 3 nj nj n 2. . h 1 n 1. . b-seg n 3. . h 1 n 1. . b-seg n 2. . h 2 Pi= i-via path is explored P 1 n 2. pin or obs n 1. b-seg

DFS-Controlled Routing with Bump & Refit n 3. . v 1 nj n 2 n 3 nj nj n 2. . h 1 n 2. . h 2 n 3. . h 1 n 1. . b-seg n 2. . h 2 Pi= i-via path is explored n 1. b-seg P 1 P 2 n 2. pin or obs n 2. h 2 P 1 n 3. v 1

DFS-Controlled Routing with Bump & Refit n 3. . v 1 nj n 2 n 3 nj nj n 2. . h 1 n 2. . h 2 n 3. . h 1 n 2. . h 2 P 1 P 2 n 2. pin or obs n 1. . b-seg Pi= i-via path is explored n 1. b-seg n 2. h 2 P 1 obs n 3. v 1 P 1 anc P 2 -P 4 obs or anc. n 1 or anc. nj

DFS-Controlled Routing with Bump & Refit n 3. . v 1 nj n 2 n 3 nj nj n 2. . h 1 n 1 P 1 n 3. . h 1 n 2. . h 2 n 1. . b-seg Pi= i-via path is explored n 1. b-seg P 2 n 2. pin or obs n 2. h 2 P 2 -P 3 P 1 obs n 3. v 1 P 1 anc P 2 -P 4 obs or anc. n 1 or anc. nj P 1 obs n 3. h 1 P 2 -P 4 obs or anc. n 1 or anc. nj

DFS-Controlled Routing with Bump & Refit n 3. . v 1 nj n 2 n 3 nj nj n 2. . h 1 n 1 P 1 n 3. . h 1 n 2. . h 2 n 1. . b-seg n 2. . h 2 Pi= i-via path is explored n 1. b-seg P 2 n 2. pin or obs n 2. h 2 P 2 -P 3 P 1 obs n 3. v 1 P 1 anc P 2 -P 4 obs or anc. n 1 or anc. nj P 1 obs n 3. h 1 P 2 -P 4 obs or anc. n 1 or anc. nj

DFS-Controlled Routing with Bump & Refit n 3. . v 1 nj n 2 n 3 nj nj n 2. . h 1 n 1. . b-seg n 3. . h 1 Pi= i-via path is explored n 2. h 1 P 2 n 2. pin or obs n 1. . b-seg n 2. . h 2 P 2 n 1. b-seg n 2. h 2 P 1 obs P 2 -P 3 P 1 obs n 3. v 1 P 1 anc P 2 -P 4 obs or anc. n 1 or anc. nj P 1 obs n 3. h 1 P 2 -P 4 obs or anc. n 1 or anc. nj

DFS-Controlled Routing with Bump & Refit n 3. . v 1 nj n 2 n 3 nj nj P 1 n 3. . h 1 n 1 Pi= i-via path is explored n 2. h 1 P 2 n 2. pin or obs n 2. . h 2 P 2 n 1. b-seg n 2. h 2 P 1 obs P 2 -P 3 P 1 obs n 3. v 1 P 1 anc P 2 -P 4 obs or anc. n 1 or anc. nj P 1 obs P 2 VGL n 3. h 1 P 2 -P 4 obs or anc. n 1 or an. nj

Characteristics of Benchmark Circuits – Width of net 2 -15 unit – Space req. btw. nets 1 - 8 unit – Base 2 x 2 tile of Mcc 1 benchmark is replicated with diff. cell sizes and diff. # of pins – Nets connected to pins randomly generated routed by using max 4 -via routing – Experiment involved routing as many nets as possible under the constraint of 2 metal layers only routing succ. rate = efficacy of router

Experimental Results

Experimental Results (Comparison of Failed Nets) • Unrouted nets are longer and wider when Std. and R&R used • DSR gets more compact layout by routing more and wider nets

Experimental Results (Comparison of Modified Nets)

Experimental Results (Global Nets)

Experimental Results (Global Nets)

Conclusions • New Incremental Routing Algorithm DSR – gridless routing – variable width/space • Produces significant impr. over Std. R&R – Via incr. of modified nets (3 (5) times less than R&R, 10% and 20%, respectively) – Higher routing success rate (Std. =10. 8 (8. 5) R&R= 4. 6 (2. 4) times worse) – Wire length (HPBB) of failed nets: Std. = 36. 7 (6. 59) R&R = 5. 1 (2. 15) times worse) – Degree of modification (~20% less modification than R&R) • Future Work – Tile-based approach to avoid congestion – Timing-driven DSR algorithm

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