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A D LP DDR RAM 3. 3 v 1. 8 v 1. 2 v 48 V Power From Bulk Supply Optical Link To DAQ System Network Interface ARM u. C USB 100 Mbit Ethernet Readout controller Block Diagram Optical Link To Another Controller (optional) Ø Det LPF Rd Wrt A D LV DC-DC Converters Clock VXO FPGA Triggers Event Data Control Status S. Hansen - CD-1 Lehman Review Links to 24 Si. PM Front End Boards 1
Si. PM Bias Generator Bias Bus Cvt Clk FR Clk S Dat 1. 8 v 1. 2 v USB LV DC-DC Converters Counter Mother Board One of 64 Channels 500 MB LPDDR RAM Parallel FLASH CFG ROM FPGA 3. 3 v 2. 5 v 1 of 4 Si. PMs Bias Bus One of 8 12 bit 80 msps ADCs/chip 48 V ARM Microcontroller with ECC RAM Link to readout Controller Bias Trim DAC Octal Ultra. Sound Processor Chan 0. . 15 Chan 16. . 31 Chan 32. . 47 Chan 48. . 63
Relevant Operating Environment Numbers: Channel count - 16000 Radiation dose – 1 E 11 neutron/cm 2, 1 Krad - in the hottest region Ambient magnetic field 100 m. T Peak rate per Si. PM 700 KHz, average rate 130 KHz Nominal Si. PM gain – 1 E 6, Zero-suppression threshold – 7 p. e. Largest expected signal – 200 p. e. Flash gate to lower voltage for ~500 ns of every 1596 ns – delivers very large signal to front end Front End Device Options Present (unofficial) default: VMM 2: Pros: Rad tolerant by design. Low power <10 m. W/ch , low readout bandwidth, (too) high density - 64 channels TDC+ADC. Serial data rate (400 mbit/s) allows the use of flash a based FPGA with built in processor with ECC memory for radiation tolerance. Inherent zero-suppression Allows for relatively small DRAM buffer (512 MB) Cons: Not designed for Si. PMs. Sensitivity too high (2 fc/m. V), shaping time too long. – poor double pulse timing Long overload recovery time, too long even for CMS – fixed in the next iteration. 10 Bit amplitude ADC one bit shy of desirable dynamic range Address long shaping times by halving channel density and ping-ponging between two inputs. Use peak finder to switch input. Worry – adding a feature not needed by primary customer
Front End Device Options, cont’d TDR default: Commercial Ultrasound chip: Pros: Reasonable power (120 m. W/ch). Fast sampling (12. 5 ns) – OK double pulse resolution. 12 bit ADC. OK density (8 channels/chip) Good overload recovery behavior Cons: Unknown radiation tolerance – must be tested. Very high bandwidth data connection (960 Mbit/s) Must monitor and refresh setup registers in case of SEUs. Cannot use flash based FPGA. Must use SRAM FPGAs, monitor and refresh FPGA configuration RAM. Use external ARM R 4 processor which has high-rel features, use for rad tolerance. Third option: QIE 11: Pros: Rad tolerant by design. Specifically designed for Si. PMs. ADC+TDC. Very large dynamic range, much more than we need. 53 MHz sampling should give OK double pulse resolution. Low readout data rate (106 mbit/s) allows the use of flash based FPGA. Good overload recovery for one polarity of signal, poor for the other. Flash gate is bi-polar transient Cons: High power - 300 m. W per channel. Low density (one channel per chip). Input scheme requires two input transmission lines. Doubles our CMB to FEB signal paths. Parallel readout, many pins – 576 LVDS pairs for 64 channels
Short term plans Buy an ultrasound demo board and do radiation tests. If it fails, one less decision to make Understand the VMM 2 chip in greater detail. Will need to talk with chip designer Keep working on those portions of the front board that are independent of the input device.