A Comparison of FET Devices Fin FETs vs

A Comparison of FET Devices: Fin. FETs vs. Traditional CMOS Walive Pathiranage Manula Randhika Pathirana, Matthew Ridder, and Luis Lopez Ruiz University of Virginia, Dept. of Electrical Engineering Dec 11, 2015

MOSFET and Fin. FET Structure • 2 D structure • Conducting channel only on the surface. • As the channel decreases, the control over the device is reduced. • • 3 D structure Conducting channel on 3 sides. Very little leakage. High potential for large improvements in power

Related Work • 22 and 45 nm technology comparisons for 6 T SRAM cells • Power reduction and faster performance 3

Our Project 16 nm technology 4

Setup

NAND 6

NAND Results CMOS Fin. FET 7

NOR 8

NOR Results CMOS Fin. FET 9

XOR 10

XOR Results 16 nm CMOS 16 nm fin. FET 11

Flip Flop 12

Flip Flop Results CMOS Fin. FET 13

4 -bit Adder 14

4 -bit Adder Results CMOS 15

4 -bit Adder Results Fin. FET 16

MUX 4 to 1 Schematic 17

MUX 4 to 1 Testbench 18

MUX Results 16 nm CMOS Technology – Transient Analysis 19

MUX Results 16 nm fin. FET Technology – Transient Analysis 20

MUX Results Delay and Power Measurements Comparisson 21

Conclusions and Future Work • Fin. FET devices show a high improvement over traditional CMOS in terms of both delay and leakage. § XOR: fin. FET 11 x faster and 8 x less leakage. § MUX: fin. FET 12 x faster and 10 x less leakage § NAND: Fin. FET 8 x faster and 3 x less leakage § Adder: Fin. FET 14 x faster and 4 x less leakage • Next steps would be to obtain access to layout and do area analysis and comparison between technologies by including parasitic effect • Despite the improvements shown, there are challenges to fully adopt this new technology: resources for modeling and designing, fabrication, cost, etc. 22