Figure 4 1 Application of commutative law of

Figure 4. 2 Application of commutative law of multiplication. Digital Fundamentals, Tenth Edition Thomas

Figure 4. 3 Application of associative law of addition. Open file F 04 -03

Figure 4. 4 Application of associative law of multiplication. Open file F 04 -04

Figure 4. 5 Application of distributive law. Open file F 04 -05 to verify.

Figure 4. 6 Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by

Figure 4. 7 Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by

Figure 4. 8 Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by

Figure 4. 9 Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by

Figure 4. 10 Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by

Figure 4. 11 Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by

Figure 4. 12 Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by

Figure 4. 13 Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by

Figure 4. 14 Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by

Figure 4. 15 Gate equivalencies and the corresponding truth tables that illustrate De. Morgan’s

Figure 4. 16 A combinational logic circuit showing the development of the Boolean expression

Figure 4. 17 Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by

Figure 4. 18 Gate circuits for Example 4– 9. Open file F 04 -18

Figure 4. 19 Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by

Figure 4. 20 Implementation of the SOP expression AB + BCD + AC. Digital

Figure 4. 21 This NAND/NAND implementation is equivalent to the AND/OR in Figure 4–

Figure 4. 22 Implementation of the POS expression (A + B)(B + C +

Figure 4. 23 A 3 -variable Karnaugh map showing product terms. Digital Fundamentals, Tenth

Figure 4. 24 A 4 -variable Karnaugh map. Digital Fundamentals, Tenth Edition Thomas L.

Figure 4. 25 Adjacent cells on a Karnaugh map are those that differ by

Figure 4. 26 Example of mapping a standard SOP expression. Digital Fundamentals, Tenth Edition

Figure 4. 27 Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by

Figure 4. 28 Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by

Figure 4. 29 Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by

Figure 4. 30 Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by

Figure 4. 31 Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by

Figure 4. 32 Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by

Figure 4. 33 Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by

Figure 4. 34 Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by

Figure 4. 35 Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by

Figure 4. 36 Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by

Figure 4. 37 Example of mapping directly from a truth table to a Karnaugh

Figure 4. 38 Example of the use of “don’t care” conditions to simplify an

Figure 4. 39 Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by

Figure 4. 40 Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by

Figure 4. 41 A 5 -variable Karnaugh map. Digital Fundamentals, Tenth Edition Thomas L.

Figure 4. 42 Illustration of groupings of 1 s in adjacent cells of a

Figure 4. 43 Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by

Figure 4. 44 A VHDL program for a 2 -input AND gate. Digital Fundamentals,

Figure 4. 45 Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by

Figure 4. 46 Seven-segment display. Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright ©

Figure 4. 47 Hexadecimal-to-7 -segment decoder for letters A through E, used in the

Figure 4. 48 Minimization of the expressions for segments a, b, and c. Digital

Figure 4. 49 Segment-b and segment-c logic circuits. Digital Fundamentals, Tenth Edition Thomas L.

Figure 4. 50 Multisim circuit screen for decoder and display. Digital Fundamentals, Tenth Edition

Figure 4. 51 Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by

Figure 4. 52 Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by

Figure 4. 53 Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by

Figure 4. 54 Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by

Figure 4. 55 Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by

Figure 4. 56 Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by

Figure 4. 57 Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by

Figure 4. 58 Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by

Figure 4. 59 Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by

Figure 4. 60 Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by

Figure 4. 61 Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by

Figure 4. 62 Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by

Slides: 62

Download presentation

Figure 4. 1 Application of commutative law of addition. Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 4. 2 Application of commutative law of multiplication. Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 4. 3 Application of associative law of addition. Open file F 04 -03 to verify. Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 4. 4 Application of associative law of multiplication. Open file F 04 -04 to verify. Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 4. 5 Application of distributive law. Open file F 04 -05 to verify. Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 4. 15 Gate equivalencies and the corresponding truth tables that illustrate De. Morgan’s theorems. Notice the equality of the two output columns in each table. This shows that the equivalent gates perform the same logic function. Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 4. 16 A combinational logic circuit showing the development of the Boolean expression for the output. Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 4. 18 Gate circuits for Example 4– 9. Open file F 04 -18 to verify equivalency. Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 4. 20 Implementation of the SOP expression AB + BCD + AC. Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 4. 21 This NAND/NAND implementation is equivalent to the AND/OR in Figure 4– 20. Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 4. 22 Implementation of the POS expression (A + B)(B + C + D)(A + C). Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 4. 23 A 3 -variable Karnaugh map showing product terms. Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 4. 24 A 4 -variable Karnaugh map. Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 4. 25 Adjacent cells on a Karnaugh map are those that differ by only one variable. Arrows point between adjacent cells. Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 4. 26 Example of mapping a standard SOP expression. Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 4. 37 Example of mapping directly from a truth table to a Karnaugh map. Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 4. 38 Example of the use of “don’t care” conditions to simplify an expression. Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 4. 41 A 5 -variable Karnaugh map. Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 4. 42 Illustration of groupings of 1 s in adjacent cells of a 5 -variable map. Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 4. 44 A VHDL program for a 2 -input AND gate. Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 4. 47 Hexadecimal-to-7 -segment decoder for letters A through E, used in the system. Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 4. 48 Minimization of the expressions for segments a, b, and c. Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 4. 49 Segment-b and segment-c logic circuits. Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.

Figure 4. 50 Multisim circuit screen for decoder and display. Digital Fundamentals, Tenth Edition Thomas L. Floyd Copyright © 2009 by Pearson Higher Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved.