80868088 Microprocessor Introduction to the processor and its

8086/8088 Microprocessor Introduction to the processor and its pin configuration

Topics • • Basic Features Pinout Diagram Minimum and Maximum modes Description of the pins

Basic Features • 8086 announced in 1978; 8086 is a 16 bit microprocessor with a 16 bit data bus • 8088 announced in 1979; 8088 is a 16 bit microprocessor with an 8 bit data bus • Both manufactured using High-performance Metal Oxide Semiconductor (HMOS) technology • Both contain about 29000 transistors • Both are packaged in 40 pin dual-in-line package (DIP)

8086/8088 Pinout Diagrams GND AD 14 AD 13 AD 12 AD 11 AD 10 AD 9 AD 8 AD 7 AD 6 AD 5 AD 4 AD 3 AD 2 AD 1 AD 0 NMI INTR CLK GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 8086 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC AD 15 A 16/S 3 A 17/S 4 A 18/S 5 A 19/S 6 BHE/S 7 MN/MX RD HOLD HLDA WR M/IO DT/R DEN ALE INTA TEST READY RESET GND A 14 A 13 A 12 A 11 A 10 A 9 A 8 AD 7 AD 6 AD 5 AD 4 AD 3 AD 2 AD 1 AD 0 NMI INTR CLK GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 8088 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC A 15 A 16/S 3 A 17/S 4 A 18/S 5 A 19/S 6 SS 0 MN/MX RD HOLD HLDA WR IO/M DT/R DEN ALE INTA TEST READY RESET BHE has no meaning on the 8088 and has been eliminated

Multiplex of Data and Address Lines in 8088 • Address lines A 0 -A 7 and Data lines D 0 -D 7 are multiplexed in 8088. These lines are labelled as AD 0 -AD 7. – By multiplexed we mean that the same pysical pin carries an address bit at one time and the data bit another time GND A 14 A 13 A 12 A 11 A 10 A 9 A 8 AD 7 AD 6 AD 5 AD 4 AD 3 AD 2 AD 1 AD 0 NMI INTR CLK GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 8088 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC A 15 A 16/S 3 A 17/S 4 A 18/S 5 A 19/S 6 SS 0 MN/MX RD HOLD HLDA WR IO/M DT/R DEN ALE INTA TEST READY RESET

Multiplex of Data and Address Lines in 8086 • Address lines A 0 -A 15 and Data lines D 0 -D 15 are multiplexed in 8086. These lines are labelled as AD 0 -AD 15. GND AD 14 AD 13 AD 12 AD 11 AD 10 AD 9 AD 8 AD 7 AD 6 AD 5 AD 4 AD 3 AD 2 AD 1 AD 0 NMI INTR CLK GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 8086 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC AD 15 A 16/S 3 A 17/S 4 A 18/S 5 A 19/S 6 BHE/S 7 MN/MX RD HOLD HLDA WR M/IO DT/R DEN ALE INTA TEST READY RESET

Minimum-mode and Maximum-mode Systems • 8088 and 8086 microprocessors can be configured to work in either of the two modes: the minimum mode and the maximum mode ü Minimum mode: Ø Pull MN/MX to logic 1 Ø Typically smaller systems and contains a single microprocessor Ø Cheaper since all control signals for memory and I/O are generated by the microprocessor. ü Maximum mode Ø Pull MN/MX logic 0 Ø Larger systems with more than one processor (designed to be used when a coprocessor (8087) exists in the system) GND AD 14 AD 13 AD 12 AD 11 AD 10 AD 9 AD 8 AD 7 AD 6 AD 5 AD 4 AD 3 AD 2 AD 1 AD 0 NMI INTR CLK GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 8086 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC AD 15 A 16/S 3 A 17/S 4 A 18/S 5 A 19/S 6 BHE/S 7 MN/MX RD HOLD HLDA WR M/IO DT/R DEN ALE INTA TEST READY RESET Lost Signals in Max Mode

Minimum-mode and Maximum-mode Signals GND AD 14 AD 13 AD 12 AD 11 AD 10 AD 9 AD 8 AD 7 AD 6 AD 5 AD 4 AD 3 AD 2 AD 1 AD 0 NMI INTR CLK GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 8086 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 Min Mode VCC AD 15 A 16/S 3 A 17/S 4 A 18/S 5 A 19/S 6 BHE/S 7 MN/MX RD HOLD HLDA WR M/IO DT/R DEN ALE INTA TEST READY RESET Vcc GND AD 14 AD 13 AD 12 AD 11 AD 10 AD 9 AD 8 AD 7 AD 6 AD 5 AD 4 AD 3 AD 2 AD 1 AD 0 NMI INTR CLK GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 8086 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC AD 15 A 16/S 3 A 17/S 4 A 18/S 5 A 19/S 6 BHE/S 7 MN/MX RD RQ/GT 0 RQ/GT 1 LOCK S 2 S 1 S 0 QS 1 TEST READY RESET Max Mode GND

8086 System Minimum mode

8086 System Maximum Mode

Description of the Pins GND AD 14 AD 13 AD 12 AD 11 AD 10 AD 9 AD 8 AD 7 AD 6 AD 5 AD 4 AD 3 AD 2 AD 1 AD 0 NMI INTR CLK GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 8086 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 Min Mode VCC AD 15 A 16/S 3 A 17/S 4 A 18/S 5 A 19/S 6 BHE/S 7 MN/MX RD HOLD HLDA WR M/IO DT/R DEN ALE INTA TEST READY RESET Vcc GND AD 14 AD 13 AD 12 AD 11 AD 10 AD 9 AD 8 AD 7 AD 6 AD 5 AD 4 AD 3 AD 2 AD 1 AD 0 NMI INTR CLK GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 8086 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC AD 15 A 16/S 3 A 17/S 4 A 18/S 5 A 19/S 6 BHE/S 7 MN/MX RD RQ/GT 0 RQ/GT 1 LOCK S 2 S 1 S 0 QS 1 TEST READY RESET Max Mode GND

RESET Operation results CPU component Contents Flags Instruction Pointer CS DS, SS and ES Queue Cleared 0000 H FFFFH 0000 H Empty

AD 0 - AD 15: Address Data Bus Data AD 0 – AD 15 Address

A 17/S 4, A 16/S 3 Address/Status A 17/S 4 A 16/S 3 Function 0 0 Extra segment access 0 1 Stack segment access 1 0 Code segment access 1 1 Data segment access

A 19/S 6, A 18/S 5 Address/Status A 18/S 5: The status of the interrupt enable flag bit is updated at the beginning of each cycle. The status of the flag is indicated through this pin A 19/S 6: When Low, it indicates that 8086 is in control of the bus. During a "Hold acknowledge" clock period, the 8086 tri-states the S 6 pin and thus allows another bus master to take control of the status bus.

S 0, S 1 and S 2 Signals S 2 S 1 S 0 0 0 0 1 1 0 0 1 0 1 Characteristics Interrupt acknowledge Read I/O port Write I/O port Halt Code access Read memory 1 1 0 Write memory 1 1 1 Passive State

QS 1 and QS 2 Signals QS 1 0 0 1 1 0 1 Characteristics No operation First byte of opcode from queue Empty the queue Subsequent byte from queue

Read Write Control Signals IO/M DT/R SSO 0 0 1 1 0 1 0 1 CHARACTERISTICS Code Access Read Memory Write Memory Passive Interrupt Acknowledge Read I/O port Write I/O port Halt

8086 Memory Addressing Data can be accessed from the memory in four different ways: • 8 - bit data from Lower (Even) address Bank. • 8 - bit data from Higher (Odd) address Bank. • 16 - bit data starting from Even Address. • 16 - bit data starting from Odd Address.

Treating Even and Odd Addresses

8 -bit data from Even address Bank MOV SI, 4000 H MOV AL, [SI+2]

8 -bit Data from Odd Address Bank MOV SI, 4000 H MOV AL, [SI+3]

16 -bit Data Access starting from Even Address MOV SI, 4000 H MOV AX, [SI+2]

16 -bit Data Access starting from Odd Address MOV SI, 4000 H MOV AX, [SI+5]

Read Timing Diagram

Write Machine Cycle

INTR (input) Hardware Interrupt Request Pin • INTR is used to request a hardware interrupt. • It is recognized by the processor only when IF = 1, otherwise it is ignored (STI instruction sets this flag bit). • The request on this line can be disabled (or masked) by making IF = 0 (use instruction CLI) • If INTR becomes high and IF = 1, the 8086 enters an interrupt acknowledge cycle (INTA becomes active) after the current instruction has completed execution.

For Discussion • If I/O peripheral wants to interrupt the processor, the “interrupt controller” will send high pulse to the 8086 INTR pin. • What about if a simple system to be built and hardware interrupts are not needed; What to do with INTR and INTA?

NMI (input) Non-Maskable Interrupt line • The Non Maskable Interrupt input is similar to INTR except that the NMI interrupt does not check to see if the IF flag bit is at logic 1. • This interrupt cannot be masked (or disabled) and no acknowledgment is required. • It should be reserved for “catastrophic” events such as power failure or memory errors.

8086 External Interrupt Connections NMI - Non-Maskable Interrupt INTR - Interrupt Request Programmable Interrupt Controller (part of chipset) NMI Requesting Device NMI 8086 CPU INTR Interrupt Logic Intel 8259 A PIC into Software Divide Error Single Step Traps

TEST (input) • The TEST pin is an input that is tested by the WAIT instruction. • If TEST is at logic 0, the WAIT instruction functions as a NOP. • If TEST is at logic 1, then the WAIT instruction causes the 8086 to idle, until TEST input becomes a logic 0. • This pin is normally driven by the 8087 coprocessor (numeric coprocessor). • This prevents the CPU from accessing a memory result before the NDP has finished its calculation

Ready (input) • This input is used to insert wait states into processor Bus Cycle. • If the READY pin is placed at a logic 0 level, the microprocessor enters into wait states and remains idle. • If the READY pin is placed at a logic 1 level, it has no effect on the operation of the processor. • It is sampled at the end of the T 2 clock pulse • Usually driven by a slow memory device

8284 Connected to 8086 Mp X 1 Ready CLK AEN 1 AEN 2 F/C RDY 1 RDY 2 R +5 V RESET KEY 8284 RES C Reset 8086 Microprocessor X 2

HOLD (input) • The HOLD input is used by DMA controller to request a Direct Memory Access (DMA) operation. • If the HOLD signal is at logic 1, the microprocessor places its address, data and control bus at the high impedance state. • If the HOLD pin is at logic 0, the microprocessor works normally.

HLDA (output) Hold Acknowledge Output • Hold acknowledge is made high to indicate to the DMA controller that the processor has entered hold state and it can take control over the system bus for DMA operation.

DMA Operation