68000 Hardware interface part 2 9206 Lecture 3

68000 Hardware interface (part 2) 9/20/6 Lecture 3 - Instruction Set - Al 1

The 68000 Hardware Architecture - 2 o o 9/20/6 Have gone over the all the pins except those dealing with memory. Memory and Peripheral Interface Synchronous Bus Control Asynchronous Bus Control Lecture 3 - Instruction Set - Al 2

Memory and Peripheral Interface o o These pins take up 44 of the 64 pins Allow for reading from and writing to main memory. The 68000 is a memory mapped architecture Memory Mapped Architecture n 9/20/6 All input and output from the processor is to a single address space shared by memory and I/O ports. You need a memory map to know where the various activities are located. Lecture 3 - Instruction Set - Al 3

Other memory interfaces o Separate memory and I/O address spaces n n n 9/20/6 Requires a few pins to differentiate when memory and when input/output is occurring as the address and data line are usually common. There are separate control pins for memory access and I/O access. Requires separate instructions for memory access and input/output to a I/O port. Common to Intel architectures. Lecture 3 - Instruction Set - Al 4

68000 Memory & Peripheral Pins o Address Bus n n n o 9/20/6 23 pins – A 01 to A 23 Address space - 223 which is how many gigs? 16 bits = 64 K 1 G = 230 20 bits = 1 M 23 bits = ? ? Address bus value indicates which 16 -bit word of memory is being addressed Lecture 3 - Instruction Set - Al 5

Data Bus o Data Bus n n n 9/20/6 16 -bits wide Bi-directional Pins on processor are tristate Word operation – all lines active Byte operation – either the high order bits or the low order bits active depending on the byte being transferred (as indicated by UDS* or LDS*) Lecture 3 - Instruction Set - Al 6

68000 Memory & Peripheral Pins o AS* - Address Strobe n o R/W n n 9/20/6 Indicates that the address bus lines are valid Read/Write(bar) Indicates the direction of the transfer Read – 1 – processor is receiving the data Write – 0 – processor is outputting the data Lecture 3 - Instruction Set - Al 7

68000 Memory & Peripheral Pins o UDS* and LDS* n n o DTACK* - data transfer acknowledge n 9/20/6 Upper data strobe and Lower data strobe Indicates which byte(s) of the word addressed are being accessed Both asserted on a word access Only one for a byte access Asserted by device being accessed to indicate that data bus is valid Lecture 3 - Instruction Set - Al 8

UDS* and LDS* control 9/20/6 Lecture 3 - Instruction Set - Al 9

Synchronous Bus Control o o Most transfers take place asynchronously 3 pins for synchronous bus control n n n 9/20/6 VPA* - Valid peripheral address VMA* - Valid memory address E – Enable output from the 68000 – A timing signal for interfacing with 6800 series peripherals Lecture 3 - Instruction Set - Al 10

Asynchronous Bus Conrol o The usual transfer protocol – CPU read cycle o Note handshake. 9/20/6 Lecture 3 - Instruction Set - Al 11

68000 Read cycle o o o 9/20/6 Protocol of the read cycle Note that this is a bus master, bus slave protocol Bus master could be a device other than CPU – same protocol. Lecture 3 - Instruction Set - Al 12

Timing diagram review o o 9/20/6 For a D F/F Actual behavior indicating timing parameters General form Alternative form indicating sequence Lecture 3 - Instruction Set - Al 13

68000 Read cycle o o o o 9/20/6 Clock is 50% duty cycle Address becomes valid AS* asserted LDS*, UDS* asserted R/W Memory responds with DTACK* Memory sends data Lecture 3 - Instruction Set - Al 14

Continued Wait states are Added until DTACK* asserted 9/20/6 Lecture 3 - Instruction Set - Al 15

Timing Diagram with parameters 9/20/6 Lecture 3 - Instruction Set - Al 16

Parameters 9/20/6 Lecture 3 - Instruction Set - Al 17

Write cycle protocol 9/20/6 Lecture 3 - Instruction Set - Al 18

Write cycle timing 9/20/6 Lecture 3 - Instruction Set - Al 19

Write cycle timing 9/20/6 Lecture 3 - Instruction Set - Al 20

Write cycle parameters 9/20/6 Lecture 3 - Instruction Set - Al 21