68 KColdfire Processor Core and ISA Computer Science

68 K/Coldfire Processor Core and ISA Computer Science & Engineering Department Arizona State University Tempe, AZ 85287 Dr. Yann-Hang Lee yhlee@asu. edu (480) 727 -7507

68 K/Coldfire Processor Core - Introduction q Starting from 6800 in 1974 v 8 -bit data and 16 -bit address CISC processor q Microcontrollers v 8 -bit: HC 05, HC 11, HC 08, RS 08 (6 -8 pins, 1 K flash, 64 byte RAM) v 16 -bit: HC 16, HC 12, S 12 1

68 K/Coldfire Processor Core - Introduction q Microprocessors v 1 st generation: 68000 (16/32) -- 1979 v 2 nd generation: 68020/68030 (fully 32 bits) -- 1984 v 3 rd generation: 68040/68050 (FPU, splict cache, fully pipelined)-- 1990 v 4 th generation: 68060 (superscalar and multiple integer pipelines, abandoned in favor of the Power. PC chips ) -- 1994 q Coldfire: a variant of 68 K starting from 1994 v “assembly source" compatible, variable-length RISC q Main differences between 68 K and Coldfire v Missing addressing modes and instructions v Non-availability of word- and byte-forms of nearly all arithmetic and logical instructions v Many instructions act only on registers, not on memory v Restrictions on available addressing modes for particular instructions v Simplification of the supervisor-level programming model 2

Coldfire Processor Core - Introduction q Architecture v Version 2/2 M – single-issue v Version 3 – single-Issue + pipelined local bus v Version 4/4 e – limited superscalar v Version 5 – fully superscalar q Coldfire cores v Synthesizable, configurable, and parameterizable q Platform: v use defined and verified set of IP blocks as the foundation for a system-on-a-Chip (So. C) design. v CF 5210 and Standard Product Platform (with crossbar switch) q Coldfire processors v based on the Coldfire cores with integration (memory, bus, and peripheral interfaces) that is common in embedded systems. 3

Coldfire CF 5210 Platform q Version 2 Coldfire CPU core plus v On-chip memory controllers v Arbiter v DMA v Interrupts v External busses v Peripherals 4

Coldfire CF 5210 Platform Usage q Differences in speed and external bus (memory) v 5274/74 at 166 Mz and 5211/12/13 at 80 MHz v SDRAM controller and external bus in 5274/5275 5

Example -- ARM Processor Core q Architecture v Versions 1 and 2 -- Acorn RISC, 26 -bit address v Version 3 – 32 -bit address, CPSR, and SPSR v Version 4 – half-word, Thumb v Version 5 q Processor cores v ARM 7 TDMI (Thumb, debug, multiplier, ICE) – version 4 T, low-end ARM core, 3 -stage pipeline v ARM 9 TDMI – 5 -stage pipeline v ARM 10 TDMI – version 5 q CPU Core: co-processor, MMU, AMBA v ARM 710, 720, 740 v ARM 920, 940 6

Data in Coldfire Memory q Alignment of bytes, words, longwords in memory v signed and unsigned q Memory and address v a flat space of 232 bytes (addressable with bit manipulations) v big-endian (1 st btye is the most significant byte) 7

Endianess Example q This has no real relevance unless data is stored as longwords and then accessed in smaller sized quantities (words or bytes). v Which byte / word is accessed will depend on the endianess of the system involved. d 0 = 0 x 11223344 11 22 33 44 move. l d 0, (a 1) Big-endian a 1 = 0 x 100 11 Little-endian 22 33 44 a 1 = 0 x 100 44 33 22 -- -- -- 11 move. b d 2, (a 1) -- -- -- d 2 = 0 x 11 11 44 d 2 = 0 x 44 8

Register Organization q The register set is derived from and directly compatible with that in 68 K family CPUs q Data registers: D 0 -D 7 v v v v Size - 32 -bits (longword) 16 -bit (word) and 8 -bit (byte) subsets Used for most data manipulation General-purpose - any data operation on any data register Operate on longwords, and bytes Depends on instruction More significant register bits unaffected by byte and word ops Mnemonics -. L, . W, . B suffixes q Examples v ADD. L D 0, D 1 - D 1 = D 0 + D 1 using all 32 register bits v MOVE. B D 0, D 1 – move the least significant 8 bits 9

Address Registers q 32 -bit registers A 0 to A 7 q Pointer registers - contain addresses of data in memory v most memory references via address registers v base and index address registers q General-purpose - perform same operations on all v operations affect all 32 bits q A 7 - stack pointer for subroutine return address v two A 7 registers - for user (USP) and supervisor (SSP) modes q Operations – v the sign-extended low-order word or the entire longword as a source operand v as a destination operand, the entire register becomes affected 10

Special-Purpose Registers q Program counter (PC) v 32 -bit address of next instruction to execute q Condition code register (CCR) v results of a previous instruction (e. g. ADD) v use to execute conditional q Status register (SR) operations (e. g. IF) v system/status byte v C - carry bit (for B, W, L v condition code register (CCR) operations) q System/status byte v V - overflow (result overflowed) v controls operating mode v Z - zero (result is zero) v S - user/supervisor mode v N - negative (result is negative) v T - trace enable v X - extend (carry bit if arithmetic v M – master/interrupt mode operations) v I 0 -I 2 - interrupt mask (current level of interrupt that interrupts) 11

Privileged States q User mode v state where user programs execute q Supervisor mode v state where operating system executes q Exceptions and interrupts switch to supervisor v user does not directly handle them q Hard reset switches to supervisor q Privileged instructions v only execute during supervisor mode v supervisor can read/write SSP, status register, and other special registers (depending on processor model) v special registers in 5211/12/13 Ø vector base register (VBR) for exception vector table Ø flash base address register (FLASHBAR) Ø RAM base address register (RAMBAR) 12

Cold. Fire Core Pipeline q Two stage instruction fetch pipeline v Instruction address generation v Instruction fetch q Three longword entry instruction buffer decouples IFP/OEP q Two stage operand execution pipeline v Decode & select/operand cycle v Address generation execute cycle 13

Example Assembly Program /* a function to sum the squares of the elements of a vector sumsq: */ void sumsq (int *sum, int size, int array[]) { int total=0; for (int i = size-1; i < 0; i--) total= total + array[i]**2; sum=total; } loop: link movem. l movea. l move. w movea. l moveq subq. l move. w mulu add. l subq. l bne move. w movem. l unlk move. l adda. l rts end a 6, #0 d 0 -d 2/a 0 -a 1, -(sp) (8, a 6), a 0 (12, a 6), d 1 (14, a 6), a 1 #0, d 0 #1, d 1 (a 0)+, d 2 d 2, d 0 #1, d 1 loop d 0, (a 1) (sp)+, do-d 2/a 0 -a 1 a 6 (sp), (10, sp) #10, sp 14

Coldfire Instruction Format q Consist of 1 to 3 words. q Operation word: v length of the instruction, v effective addressing mode, v operation to be performed. q Up to 2 extension words, including v conditional predicates, v immediate operands, v extensions to the effective addressing mode v branch displacements, etc. 15

Coldfire Addressing Mode 16

Coldfire Instructions q Data movement v move to transfer byte, word, and longword operands from memory to memory, memory to register, register to memory, and register to register. q Program control v branch, jump, call, and return q Integer arithmetic -- add, adda, cmp, div, mul, sub, etc q Floating-point arithmetic (no FPU in 5211/5212/5213) q Logical operations v and, or, not, eor q Shift operations q Bit manipulation q System control v move to(from) SR or USP, RTE, TRAP, HALT, STOP q Cache maintenance (no cache in 5211/12/13) 17

Stacks q A stack is an area of memory which grows as new data is “pushed” onto the “top” of it, and shrinks as data is “popped” off the top. q Two pointers define the current limits of the stack. v A base pointer (frame pointer): used to point to the “bottom” of the stack (the first location). v A stack pointer: used to point the current “top” of the stack. PUSH {1, 2, 3} SP POP 3 2 SP BASE SP 1 BASE 2 1 Result of pop = 3 BASE 18

Stack Operation q Traditionally, a stack grows down in memory, with the last “pushed” value at the lowest address. v Some CPU (e. g. ARM) also supports ascending stacks which grows up through memory. q The value of the stack pointer can either: v Point to the last occupied address (Full stack) and so needs predecrementing (i. e. before the push) v Point to the next occupied address (Empty stack) and so needs postdecrementing (i. e. after the push) q Stack type: v Full Descending stack v Full Ascending stack. v Empty Descending stack v Empty Ascending stack q 68 K/Coldfire use full descending stacks. 19

Stacks and Subroutines q One use of stacks is to create temporary register workspace for subroutines. q Any registers that are needed can be pushed onto the stack at the start of the subroutine and popped off again at the end so as to restore them before returning to the caller : movem. l d 0 -d 2/a 0 -a 1, -(sp). . . . (sp)+, d 0 -d 2/a 0 -a 1 ; push registers ; pop registers q Push and pop return address (the current PC when calling a subroutine) v JSR: SP – 4 → SP; next. PC → (SP); Destination Address → PC v RTS: (SP) → PC; SP + 4 → SP 20