640251 Lecture 15 Serial Communications AVR USART Universal

640251 Lecture 15 • Serial Communications • AVR USART – Universal Synchronous Asynchronous Receiver Transmitter (ACIA: Asynchronous Communications Interface Adapter) • • • The AVR’s Serial Port Serial Data Formats - RS 232, SPI IBM PC UART: The 16550 & 16554 RS 232 / ITU V. 24 / EIA 232 Sample Interrupt Service Routine (ISR)

Serial Data Transmission (1) • Serial I/O is the transmission of data over a single communication line. – Cheaper than parallel – Data is moved sequentially one bit at a time. – Requires a conversion from parallel data format to serial format. • This conversion is normally performed by a shift register driven by a clock.

Serial Data Transmission (2) • At the receiving end, data must be reconstructed back into parallel format. • Some method is required to identify bit boundaries. • i. e. : how do you differentiate between 000 and 0000?

Serial communications Devices to perform serial communications have various names - which could be thought of as synonyms: UART: Universal Asynchronous Receiver Transmitter USART: Universal Synchronous Asynchronous Receiver Transmitter ACIA Asynchronous Communications Interface Adapter ACE - Asynchronous Communications Element The UART performs serial-to-parallel conversions on data received from a peripheral device or modem and parallel-to-serial conversion on data received from its CPU. The CPU can read the UART status at any time.

Serial Data Transmission (3) • Two methods: • Synchronous Transmission – Use a common clock to synchronise the receiver with the transmitter. – Therefore requires a separate tine to carry the clock. • Asynchronous Transmission – The receiver and transmitter has separate, independent, accurate local clocks.

Asynchronous Serial Data Transmission (1) • RS 232 Voltage Levels & Data Format – Line Transceiver with Charge Pump • MAX 232 chips. – Create +10 V & - 10 V from 5 V input. • Serial Data Format • Start Bit, Data Bits, Parity, Stop Bits • Errors: Framing, Overrun, False Start • The 6850 ACIA (Asynchronous Communications Interface Adapter) UART (Universal Asynchronous Receiver Transmitter) or ACE (Asynchronous Communications Element) – AKA: • The RS 232 Transmission Distance Limits

Serial communications Typical Simple 2 -wire (plus ground) serial connection

USART - Control and Status There are two identical USARTS in the ATMEGA 128. Each USART has three control & status registers labelled UCSRn. A, UCSRn. B and UCSRn. C, where n is 0 for USART 0 or 1 for USART 1. I. e. The Status Register for USART 0 is UCSR 0 A, UCSR 0 B and UCSR 0 C, and USART 1 is UCSR 1 A, UCSR 1 B and UCSR 1 C.

UCSRn. A RXCn is a flag set when data is received. TXCn is a flag set when the data frame has been sent. UDRE is a flag set when the User Data Register is Empty FEn - Framing Error DORn - Data Over. Run - (Data has been lost) UPEn - Is set to one if the received character had Parity Error U 2 Xn - Double the USART transmission speed MPCMn - Multi. Processor Communication Mode When the frame-type-bit (the 9 th bit) is set to one, the frame contains an address. When the frame type bit is zero the frame is a data frame. In this mode, the address frames only are received, data frames are discarded unless the address previously matched.

UCSRn. B RXCIEn RX (Receive) Character Interrupt Enable. TXCIEn TX (Transmit) Character Interrupt Enable UDRIE - User Data Interrupt Enable RXENn - Set - enables the USARTn Receiver. The Receiver will override normal port operation for the Rx. Dn pin when enabled.

UCSRn. B TXENn - enables the USARTn Transmitter. The Transmitter will override normal port operation for the Tx. Dn pin when enabled. The disabling of the Transmitter (writing TXENn to zero) will not become effective until ongoing and pending transmissions are completed. • RXB 8 n: Receive Data Bit 8 - is the ninth data bit of the received character. . Must be read before reading the low bits from UDRn. • TXB 8 n: Transmit Data Bit 8 - is the 9 th data bit in the character to be transmitted when operating with serial frames with 9 data bits. Must be written before writing the low bits to UDRn.

UCSRn. C There are two identical USARTS in the ATMEGA 128. Each USART has three control & status registers labelled UCSRn. A, UCSRn. B and UCSRn. C To indicate that the registers naming is the same, the letter n is used where a 0 (for USART 0) or 1 (for USART 1) would be. Status Register C - UCSRn. C. I. e. Status Register for USART 1 is UCSR 1 C

USART - Data Frame Format The AVR USART can transmit and receive 30 various combinations: 1 start bit; 5 to 9 data bits; even, odd or no parity, and 1 or 2 Stop bits.

USART - Data Frame Format The three bits - USART Character Si. Ze (UCSZ 2: 0) - select the number of data bits in the frame.

USART - Transmit The USARTn Transmit Data Buffer register and USARTn Receive Data Buffer Registers share the same I/O address referred to as UDRn (USARTn Data Register n). The Transmit Data Buffer Register (TXBn) will be the destination for data written to the UDRn Register location.

USART - Transmit The transmit buffer can only be written when the UDREn flag in the UCSRAn Register is set. Data written to UDRn when the UDREn flag is not set, will be ignored by the USARTn Transmitter. When data is written to the transmit buffer, and the Transmitter is enabled, the Transmitter will load the data into the Transmit Shift Register when the Shift Register is empty. Then the data will be serially transmitted on the Tx. Dn pin.

USART - Transmit & Receive Reading the UDRn Register location will return the contents of the receive data buffer register (RXBn). The receive buffer consists of a two level FIFO. The FIFO will change its state whenever the receive buffer is accessed. Due to this behavior of the receive buffer, do not use read modify write instructions (SBI and CBI) on this location. Be careful when using bit test instructions (SBIC and SBIS), since these also will change the state of the FIFO.

USART 0 & USART 1 Config UART 0 Control and Status Registers: UART 1 Control and Status Registers:

Clock Synchronisation (1) • The receiver phase locks its local clock to the transmitter's clock by detecting the start bit and stop bits of a serial frame. • Thus it does not require a separate clock line as the data line contains timing information. • If the data is sampled in the mid-point of each bit the clock error less than to 5% can be tolerated with communication remaining errorfree between transmitter and receiver.

RS 232 - Data Format

Clock Synchronisation (2) • Start bit signifies the beginning of the frame • Stop bit(s) identify the end of the frame – If the stop bits are received incorrectly it is assumed that the receiver’s clock has drifted out of phase, or some other error has occurred, and a FRAMING ERROR is declared

Communication Terminology • The rate at which data is transmitted is called the bit-rate • Bit-rate is measured in bits per second. • Baud rate refers to the rate per second of the bit symbols used to transmit the serial data. • i. e. : Baud Rate includes the synchronisation items: start bit & stop bit(s). For example: If using 10 bit symbols per 8 bit character at 9600 baud equates to a bit rate of 7680 data bits per second (or 960 Bytes per second).

Serial Data Bit Error Detection • In any data transfer there is the potential for bit-errors. Parity can be used as a check that the correct bit pattern is received. • Parity calculation involves adding the “ 1” bits in a frame together. • Even Parity – Adding all bits in frame + parity_bit => ‘ 0’ • Odd Parity – Adding all bits in frame + parity_bit => ‘ 1’

Serial Data Bit Error Detection

Bit Error Rate (BER) (1) • The Bit Error Rate - Probability of bit error - is the number of bit errors measured at the receiver through a communication system. The transmission channel may be Radio, Optical Fibre, Copper Cable, etc. • In analog communications the important unit of measure is the Signal to Noise ratio. • These measures are useful to characterise a system and can be measured or simulated.

Bit Error Rate (BER) (2) • If the quality of the system is high, the single bit error rate may be measured in years. In this case a single parity bit would be sufficient to determine data errors & retransmission could recover the correct data. • The probability of double-bit errors would become negligible. Double-bit errors cannot be detected using a single parity bit.

Improving Noise Immunity • One way of improving noise immunity: sample multiple times through each bit and at each sample time, check the status of each bit. Take the most common value of the sample as the bit value.

Bilby Schematic

AVR to USART Connections

USART Syncyronous/Asynchronous The USART supports four modes of clock operation: 1. Normal Asynchronous, 2. Double-Speed Asynchronous, 3. Master Synchronous, and 4. Slave Synchronous mode. The UMSEL bit in USART Control and Status Register C (UCSRC) selects between asynchronous and synchronous operation. Double speed (Asynchronous mode only) is controlled by the U 2 X found in the UCSRA Register. When using Synchronous mode (UMSEL = 1), the Data Direction Register for the XCK pin (DDR_XCK) controls whether the clock source is internal (Master mode) or external (Slave mode). The XCK pin is only active when using Synchronous mode.

AVR USART

AVR USART CLOCK CIRCUIT

USART Clock Signals Signal descriptions: txclk Transmitter clock. (Internal Signal) rxclk Receiver base clock. (Internal Signal) Slave Synchronous mode operation only: xcki Input from XCK pin (internal Signal). Master Synchronous mode operation only: xcko Clock output to XCK pin (Internal Signal). fosc XTAL (Crystal) pin frequency (System Clock).

AVR USART BAUD RATE

AVR USART BAUD RATE

USART Baud Rate Setup

USART Synchronous Mode

USART Transmit Character Code The following code examples show a simple USART transmit function based on polling of the Data Register Empty (UDRE) flag. When using frames with less than eight bits, the most significant bits written to the UDR are ignored. The USART has to be initialised before the function can be used. For the assembly code, the data to be sent is assumed to be stored in Register R 16

USART Transmit Character Code

USART Transmit Complete Flag The Transmit Complete (TXC) flag bit is set one when the entire frame in the Transmit Shift Register has been shifted out and there are no new data currently present in the transmit buffer. The TXC flag bit is automatically cleared when a transmit complete interrupt is executed, or it can be cleared by writing a one to its bit location. The TXC flag is useful in half-duplex communication interfaces, like RS 485, where a transmitting application must enter receive mode and free the communication bus immediately after completing the transmission.

USART Parity Generator The parity generator calculates the parity bit for the serial frame data. When parity bit is enabled (UPM 1 = 1), the transmitter control logic inserts the parity bit between the last data bit and the first stop bit of the frame that is sent.

USART Parity Generator The parity bit is calculated by performing an exclusive-or of all the data bits. If odd parity is used, the result of the exclusive or is inverted. If parity is disabled, UPM 1=0, then no parity bit is transmitted.

USART Receive Character Code

Serial Data Bit Sampling • The signal is sampled by the ACIA in the middle of each bit period.

Synchronous Serial Data Transmission (4) • Synchronous Transmission is used with the Serial Peripheral Interface (SPI) • Uses 4 wires: – Clock – Data – Select# – Ground

Serial Peripheral Interface (SPI) During an SPI transfer, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). A serial clock line synchronises shifting and sampling of the information on the two serial data lines. A slave select line allows individual selection of a slave SPI device; slave devices that are not selected do not interfere with SPI bus activities. On a master SPI device, the slave select line can optionally be used to indicate a multiple-master bus contention.

Serial Peripheral Interface (SPI) The SPI can be used to add an extra 8 bit output port using an 8 -bit shifter and latches. Master. Out. Slave. In MOSI (Serial Data) -> Pin 14 (MSB sent first) Clock ->Pin 11 SS# = Pin 12 = Low during transmission Reset# = Pin 10 = 5 V OE# = Pin 13 = 0 V

Serial Peripheral Interface (SPI) From ATMEGA 128 Manual Page 164

Serial Peripheral Interface (SPI)

AVR SPI Control Bits • Refer PP 151 -157 - Embedded C Programming, see also P 167 of ATMEGA 128 full datasheet. • SPCR - SPI Control Register • SPIE - SPI Interrupt Enable Mask Bit (1 = enable) • SPE - SPI Enable = 1 to enable SPI • DORD - Data ORDer Bit If DORD = 0, SPI transmits MSB first, else (DORD = 1) transmits LSB first

AVR SPI Control Bits • CPOL - Clock Polarity • CPHA - Clock Phase - determines if data is latched on the Leading Edge (0) / Trailing (1) edge of SCK • SPR 1: SPR 0 Spi PRescaler (SPI Frequency) – – 00 = System clock divided by 4 01 = System clock divided by 16 10 = System clock divided by 64 11 = System clock divided by 128

Serial communications

Serial communications • The EIA RS-232 interface standard defines the connector type, pin numbers, line names, and signal levels used to connect data terminal equipment to data communications equipment for the purpose of transmitting and receiving data. • The ITU V. 24 interface standard is equivalent to the RS-232 C standard; therefore, the descriptions of the EIA standards also apply to the CCITT standards.

Establishing A Serial Communications Link

Serial communications

Serial communications

Modern Serial communications The 16 C 550 x are functional upgrades of the 16 C 450 - equivalent to the 16 C 450 on power up, but can be placed in an alternate FIFO mode. The automatic FIFO mode relieves the CPU of excessive software overhead by buffering received and transmitted characters. The receiver and transmitter FIFOs store up to 16 bytes including three additional bits of error status per byte for the receiver FIFO.

Modern Serial communications In the FIFO mode, there is a selectable autoflow control feature that can significantly reduce software overload and increase system efficiency by automatically controlling serial data flow using RTS output and CTS input signals.

Automatic Flow Control ACE - Asynchronous Communications Element ACIA - Asynchronous Communications Interface Adapter UART - Universal Asyncronous Receiver Transmitter

RS 232 Pin Descriptoions DTE (Data Terminal Equipment eg: Computers & Terminals) DTE Pin Descriptions:

RS 232 Cables DCE to DTE Straight Through Computer to Modem Cable

RS 232 Cables Popular Wiring Methods for RS 232 DTE to DTE “Null Modem” - Eg “Laplink”

RS 232 Cables DTE to DTE “ 3 -Wire Null Modem” Serial Terminal to Computer Cable. Requires XON-XOFF flow control

RS 232 Cables 9 Pin to 25 Pin Connector DTE-DTE cable

Serial communications Typical 3 -wire serial connection

Transmission Distance (1) • RS 232 Communications has limited slew rate to decrease EMI radiation. • The slew rate is due to driver current limiting and capacitance between the wires. • The longer the wire, the greater the capacitance. • Cable with capacitance of 40 p. F/m => 100 m = 4 n. F.

Transmission Distance (2) Speed versus distance limitations for EIA/TIA-232. Data Rate (baud) Distance (metres) 2400 65 4800 34 9600 16 19200 8 38400 4 57600 3 114200 1. 5

IBM PC Serial communications 16550 UART Configuration

Serial communications 16550 UART BAUD RATE Generation using a 3. 072 -MHz Crystal

Serial communications 16550 UART BAUD RATE Generation using a 1. 8432 MHz Crystal

Serial communications 16550 UART Configuration At IO Address COM 1 3 F 8. . 3 FF, COM 2 2 F 8. . 2 FF, COM 3 3 E 8. . 3 EF, COM 4 2 F 8. . 2 FF

Serial communications Interrupt Enable Register (IER) The IER enables each of the five types of interrupts and enables INTRPT in response to an interrupt generation. The IER can also disable the interrupt system by clearing bits 0 through 3. The contents of this register are summarised in the previous table

Serial communications Interrupt Identification Register (IIR) P 1 The ACE has an on-chip interrupt generation and prioritization capability. The ACE provides four prioritized levels of interrupts: Priority 1 - Receiver line status (highest priority) Priority 2 - Receiver data ready/receiver character time-out Priority 3 - Transmitter holding register empty Priority 4 - Modem status (lowest priority) When an interrupt is generated, the IIR indicates that an interrupt is pending and encodes the type of interrupt in its three least significant bits (bits 0, 1, and 2).

Serial communications Interrupt Identification Register (IIR) P 2 Detail on each bit is as follows: Bit 0: When bit 0 is cleared, an interrupt is pending Bits 1 and 2: These two bits identify the highest priority interrupt pending as indicated in the previous table. Bit 3: This bit is always cleared in 16 C 450 mode. In FIFO mode, bit 3 is set with bit 2 to indicate that a time-out interrupt is pending. Bits 4 and 5: not used (always cleared). Bits 6 and 7: These bits are always cleared in 16 C 450 mode. They are set when bit 0 of the FIFO control register is set.

Serial communications Line Control Register (LCR) In addition, the programmer is able to retrieve, inspect, and modify the contents of the LCR; this eliminates the need for separate storage of the line characteristics in system memory. Bits 0 and 1: Number of bits in each serial character. 00=5 bits, 01=6 bits, 10=7 bits, 11=8 bits Bit 2: Specifies either 1, 1. 5 or 2 stop bits If Bit 3=: parity bit is generated in transmitted data between the last data word bit and the first stop bit. In received data parity is checked. If Bit 3=0: no parity is generated or checked.

Serial communications Line Control Register (LCR) When parity is enabled and: Bit 4=1 Even Parity - An even number of logic 1 s in the data and parity bits is selected. Bit 4=0 odd parity - An odd number of logic 1 s is selected. Bit 5=1 Stick Parity. The parity bit set to 0. Bit 5=0 Stick parity is disabled.

Serial communications Line Control Register (LCR) Bit 6: Break control bit. Bit 6 is set to force a break condition; i. e. , a condition where SOUT is forced to the spacing (cleared) state. Bit 7: Divisor Latch Access Bit (DLAB). Bit 7 must be set to access the divisor latches of the baud generator during a read or write. Bit 7 must be cleared during a read or write to access the receiver buffer, the THR, or the IER.

Serial communications Line Status Register (LSR) Bit 0: Data Ready (DR) indicator for the receiver. DR is set whenever a complete incoming character has been received and transferred into the RBR or the FIFO. DR is cleared by reading all of the data in the RBR or the FIFO. Bit 1 : Overrun Error (OE) indicator. When OE is set, it indicates that before the character in the RBR was read, it was overwritten by the next character transferred into the register.

Serial communications Line Status Register (LSR) Bit 2: Parity Error (PE) indicator. When PE is set, it indicates that the parity of the received data character does not match the parity selected. In the FIFO mode, this error is associated with the particular character in the FIFO to which it applies. This error is revealed to the CPU when its associated character is at the top of the FIFO. Bit 3: Framing Error (FE) indicator. When FE is set, it indicates that the received character did not have a valid (set) stop bit. Bit 4: Break Interrupt (BI) indicator. When BI is set, it indicates that the received data input was held low for longer than a full-word transmission time.

Serial communications Line Status Register (LSR) Bit 5: Transmit Hold Register Empty (THRE) indicator. THRE is set when the THR is empty, indicating that the ACE is ready to transmit a new character. Bit 6: Transmitter Empty (TEMT) indicator. TEMT bit is set when the THR and the TSR are both empty. When either the THR or the TSR contains a data character, TEMT is cleared. In the FIFO mode, TEMT is set when the transmitter FIFO and shift register are both empty. Bit 7: Used In the FIFO mode to indicate an error condition in the FIFO buffer.

Serial communications Modem Control Register (MCR) Bit 0: This bit (DTR) controls the DTR output. Bit 1: This bit (RTS) controls the RTS output. Bit 2: This bit (OUT 1) controls OUT 1, a userdesignated output signal. Bit 3: This bit (OUT 2) controls OUT 2, a userdesignated output signal. Bit 5: Auto. Flow Control Enable (AFE). When set, the autoflow control is enabled.

Serial communications Modem Control Register (MCR) Bit 4=1 Local Loop Back feature for diagnostic testing. The transmitter SOUT is set high. The receiver SIN is disconnected. The output of the TSR is looped back into the receiver shift register input. -The four modem control inputs (CTS, DSR, DCD, and RI) are disconnected. – The four modem control outputs (DTR, RTS, OUT 1, and OUT 2) are internally connected to the four modem control inputs. – The four modem control outputs are forced to the inactive (high) levels.

Acknowledgements • I used Altium Protel 98 and Protel DXP to create these schematic diagrams • ATMEL ATMEGA 128 Reference Manual • IEEE Electronics Engineers’ Handbook, 4 th Edn, Donald Christiansen - Definitions of BAUD & BER