4 W DCDC converter Specifications TECHNICAL FEATURES Power

4 W DC/DC converter Specifications • TECHNICAL FEATURES : – Power : 4 W – Input Voltage : 22 V to 37 V – Output Voltage : One Adjustable Output above 3 adjustable ranges – 2, 5 V to 4 V/1, 2 A for a 3, 3 V Output, – 3, 5 V to 6 V/0, 8 A for a 5, 0 V Output, – 8, 5 V to 14 V/0, 33 A for a 12, 0 V Output. – Efficiency : 72 % Min – Protections : Primary Undervoltage lockout, Output regulation from 0 to 100% load, Permanent output current limitation – Telecommand : Inhibit function Power layer – Switching frequency : 330 KHz • PACKAGING : – Dimensions : 32 x 21 x 10, 5 mm – Weight : 20 g. Transformer and coils layer Regulation layer

4 W DC/DC converter Electrical tests Breadboard 3 D module Bi. Cmos Bipolar Bi. Cmos 1ère version* 5 V 3 D module 12 V 3. 3 V Bipolar 1ère version* 5 V 12 V 75. 5 78. 7 64. 9 67. 9 72. 7 0. 17 0. 4 0. 64 0. 38 0. 10 0. 54 0. 86 0. 9 0. 46 0. 33 0. 30 0. 71 0. 44 0. 2 0. 73 0. 17 1. 21 332 190 580 400 100 0 ref -2. 9 -2. 1 -4. 3 -3. 2 ref 228 178 132 382 273 231 3. 3 V 5 V 12 V 3. 3 V Efficiency (%) 72. 7 77. 6 80. 8 69. 2 71. 2 75. 9 69. 8 Line regulation (%) 0. 02 0. 01 0. 02 Load regulation (%) 0. 04 0. 06 0. 03 Regul T° (%) 0. 40 0. 38 0. 29 Spikes (m. Vpp) 60 56 80 Delta Efficiency (%) ref ref ref Delta Loss (m. W) ref ref ref ð Efficiency of 3 D DC/DC Converter between 78, 7 % for the Bi. CMOS 12, 0 V and 64, 9 % for the Bipolar 3, 3 V ð Some Efficiency loss may be due to 3 D Module plating thickness and output voltage range programming possibility (impedance mismatch and loss in the planar transformer)

4 W DC/DC converter Radiation Tests • DC/DC Reference. Parametric Bipolar 3, 3 V Bipolar 12, 0 V Bi. CMOS 3, 3 V Bi. CMOS 12, 0 V TID Level (Krads) 50 50 24 15 Functional TID Level (Krads) 40 24 – Radiation Tolerance of 3 D DC/DC Converter between 15 Krads for the Bi. CMOS 12, 0 V and 50 Krads for the Bipolar 3, 3 V and 12, 0 V – Radiation Performance of the 3 D Module significantly better than the individual components (example : The Bi. CMOS PWM driver was out of the range at 5 Krads) – Heavy ions tests will be completed by end 2004. Ø GLOBALLY SATISFACTORY RESULTS AND START OF THE 10 W DC/DC CONVERTER DEVELOPMENT IN 2003 UNDER ESA CONTRACT.

DC/DC Converters using 3 D Plus technology 10 W DC/DC converter • Development of the 10 W DC/DC converter started with an ESA contract (design by GAIA and packaging by 3 D PLUS) – Minimum change introduced in the 10 W converter parts list (compared to the 4 W converter) – Based on 4 W study, only Bipolar technology was implemented – Topology design for 5 V only (evolution to 3, 3 V, 10 V, 12 V and 15 V with minor modifications) – TID and Heavy Ions tests to be performed at two levels : • Individual test of the critical components • Test at Final Product level

10 W DC/DC converter Specifications • TECHNICAL FEATURES : – – – – Power : 10 W Input Voltage : 22 V to 37 V Output Voltage : One Adjustable Output 5, 0 V/2 A Output Ripple : 50 m. Vpp Set Point Accuracy : +/- 2% Line Regulation : +/- 0, 6 % Load Regulation : +/- 0, 6 % Efficiency : > 75 % Full Load – Protections : - Primary Under Voltage Off/On threshold 18 V/20 V, - Output regulation from 0 to 100% load (Permanent), - Permanent Output Current limitation – On/Off Telecommand – Master/Slave parallelization possibility for high Power requirements (Synchronization) – Input Filter (differential mode) – EMI (MIL-STD-416 C) with external filter – Isolation 100 MOhm @ 500 V • PACKAGING : – Dimensions : 40 x 26 x 12 mm – Weight : 45 g.

10 W DC/DC converter Development progress status • Breadboard fully compliant to specification • 3 D DC/DC converter design completed and 5 prototypes under manufacturing • 3 D Modules (5) to be tested by end 2004 • Radiation tests : – TID test to be performed in November 2004 – Heavy Ions test on stand alone components are planned for november 2004 – Heavy Ions test on DC/DC Converter are planned for Q 1/ 2005

4 W and 10 W DC/DC converters Availability DC/DC Converter Power 3, 3 V 5, 0 V 10 W 12, 0 V 15, 0 V 3, 3 V 4 W 5, 0 V 12, 0 V 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Product Available Off-the-Shelf with EM and FM quality grade Product Under Development Product to be developed with minor topology changes Output Voltage (V)

Background of 3 D Plus Packaging Technology ESA/CNES Capability Approval Methodology • The capability Approval sequence of events : – Evaluation testing phase – Process Identification Document (PID) – Approval testing phase • Implementation with the 3 D Plus stacking technology: a coordinated effort of ESA and CNES : – Evaluation phase and PID Draft completed in august 2001 • • Definition of material and processes to be evaluated Design of the test structure and PID draft Manufacturing of test structures and Evaluation testing Complementary Evaluation testing by NASA-GSFC – Approval phase started in September 2001 • Manufacturing of test structures according to PID (completed feb. 2004) • Testing phase (completed april 2004) • Completion of PID and associated procedures (outstanding action)

Evaluation Phase Technology Domain 4 ) Layers stacking 5) Cube Molding 1) Flex Design 7) Cube plating (Ni+Au) 2) Component assembly 3) Circuit Test & Screening 8) Circuit interconnection by laser grooving 6) Cube Sawing 9) Cube Test & Screening

Evaluation Phase CESAR = Cnes ESA th. Ree d-plus Flex 5 Flex 6 Flex 4 Flex 7 Flex 3 Flex 8 Flex 2 Flex 9 Flex 10 CESAR 3 D module : 114 I/O

Evaluation Phase CESAR = Cnes ESA th. Ree d-plus – CESAR included 4 TSOP 64 Mb, 8 chip capacitors, 8 chip resistors, 2 thermal sensors, 2 mechanical constraint sensors. CORROSION CHIP Film 10 2 x R 0505 – 10 internal layers + Leadframe layer 2 x R CONSTRAINT CHIP 1206 Film 9 TSOP 64 Mb DRAM Film 8 – Dimensions : 26 x 15 x 16, 2 mm TSOP 64 Mb DRAM – Number of I/Os : 114 – Flex assembly technologies involved: * Epoxy attach and Wire bonding * hand soldering 2 x C 0805 THERMAL CHIP Film 6 2 x R 0505 2 x R CONSTRAINT CHIP 1206 TSOP 64 Mb DRAM Film 5 Film 4 THERMAL CHIP – EEE Components packages involved: * Bare silicon die (PMOS 4 test chip and ACM Strain gauges) * TSOP type II (64 Mb DRAM EDO) * Ceramic and Tantalum capacitors * Resistors chips Film 7 2 x C 1210 TSOP 64 Mb DRAM 2 x C Film 3 Tantal Film 2 Film 1 CORROSION CHIP Grid 0

Evaluation Phase Test Plan successfully accomplished

Approval Phase Flow 1 : TSOP Stacking Process 4 ) Cube Molding 6 ) Cube Plating ( Ni + Au ) 1 ) Package Selection and Procurement ( TSOP, …) 7 ) Circuit interconnection by laser grooving 2 ) Component Pins de-bending 3 ) Components Stacking 5 ) Cube Sawing 8 ) Cube Test & Screening

Approval Phase Flow 2 : Flex Stacking Process 4 ) Layers Stacking 5 ) Cube Molding 1 ) Flex Design 7 ) Cube Plating ( Ni + Au ) 2 ) Components attachment 3 ) Circuit Test & Screening 8 ) Circuit interconnection by laser grooving 6 ) Cube Sawing 9 ) Cube Test & Screening

For Full NASA Report on 3 D Plus Packaging Evaluation see: http: //nepp. nasa. gov/Doc. Uploads/64 CB 4357 -A 232 -4136 -A 4 EAE 5 AA 219 AD 1 A 7/Final. Report_Eval_of_3 Dplus_CESAR_Cube_121201. pdf