4 Ch Logic Gate Prof Seewhy Lee Presents

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4. Ch Logic Gate Prof. Seewhy Lee Presents

4. Ch Logic Gate Prof. Seewhy Lee Presents

2. NOT Gat e / Buf fer Gat e

2. NOT Gat e / Buf fer Gat e

PSpice

PSpice

3. AND Gat e

3. AND Gat e

PSpice

PSpice

4. OR Gat e

4. OR Gat e

PSpice

PSpice

Majority Circuit

Majority Circuit

5. NAN D G ate

5. NAN D G ate

6. NOR Gat e

6. NOR Gat e

7. XOR Gat e

7. XOR Gat e

8. XNO R G ate

8. XNO R G ate

§ 주요 디지털 IC 계열별 특성표 t. PHL 7400 74 S 00 74 LS

§ 주요 디지털 IC 계열별 특성표 t. PHL 7400 74 S 00 74 LS 00 74 ALS 00 74 F 00 74 HC 00 74 ACT 00 t. PLH VOH (max) (min) [V] [ns] 22 15 2. 4 4. 5 5 2. 7 15 15 2. 7 11 8 3 5 4. 3 2. 5 23 23 3. 84 8 6. 5 4. 4 9 7 4. 4 VOL (max) [V] 0. 4 0. 5 0. 33 0. 1 VIH (min) [V] 2 2 2 3. 15 2 t. PHL : L에서 H로 변할 때의 전파지연시간 VIL (max) [V] 0. 8 0. 9 1. 35 0. 8 IOH (max) [m. A] -0. 4 -1 -4 -75 IOL (max) [m. A] 16 20 8 8 20 4 75 75 IIL (max) [m. A] -1. 6 -2 -0. 4 -0. 1 -0. 6 t. PLH : H에서 L로 변할 때의 전파지연시간 VOH : 논리 레벨 H일 때 출력전압 VOL : 논리 레벨 L일 때 출력전압 VIH : 논리 레벨 H일 때 입력전압 VIL : 논리 레벨 L일 때 입력전압 IOH, IOL, IIH, IIL : 위와 같을 때 전류 IIH (max) [ A] 40 50 20 20 20

§ TTL/CMOS Family 이름 규칙 패키지 외형 N : Plastic DIP J : Ceramic

§ TTL/CMOS Family 이름 규칙 패키지 외형 N : Plastic DIP J : Ceramic DIP W : Flat Pack 제조회사 SN : Texas Instrument MC : Motorola DM : National Semiconductor IM : Intersil N : Signetics MM : Monolithic Memories P : Intel H : Harries F : Fairchild AM : Advanced Micro Devices CD : RCA HD : Hitach DN/MN : Mitsubishi MB : Fujitsu TC : Toshiba HY : Hyundai GD : Gold. Star K- : Samsung 시리즈명 74 : TTL 40 : CMOS 기능에 따른 고유번호 회로타입 S : High Speed Schottky L : Low Power LS : Low Power Schottky H : High Spees F : Fast HC : High Speed CMOS(CMOS compatible) HCT : High Speed CMOS TTL(LS TTL compatible) AC : Advanced AS : Advanced Schottky ALS : Advanced Low Power Schottky

Thanks for your attention~!! Prof. Seewhy Lee

Thanks for your attention~!! Prof. Seewhy Lee

7 Ch Prof Seewhy Lee Presents 2 fulladder7 Ch Prof Seewhy Lee Presents 2 fulladder
6 Ch Prof Seewhy Lee Presents FIGURE 66 Ch Prof Seewhy Lee Presents FIGURE 6
3 h C Prof Seewhy Lee Presents Thanks3 h C Prof Seewhy Lee Presents Thanks
Topics Logic gate delay n Logic gate powerTopics Logic gate delay n Logic gate power
0 1 h C Counter Prof Seewhy Lee0 1 h C Counter Prof Seewhy Lee
17 3 RL Circuit Prof Seewhy Lee Description17 3 RL Circuit Prof Seewhy Lee Description
3 h C Digital Code Prof Seewhy Lee3 h C Digital Code Prof Seewhy Lee
8 h C AC Circuit Prof Seewhy Lee8 h C AC Circuit Prof Seewhy Lee
Flow Gate Flow Gate UTM Flow Gate FlowFlow Gate Flow Gate UTM Flow Gate Flow
GATE General Architecture for Text Engineering GATE GATEGATE General Architecture for Text Engineering GATE GATE
Flow Gate Flow Gate UTM Flow Gate FlowFlow Gate Flow Gate UTM Flow Gate Flow
Contemporary Logic Design TwoLevel Logic Gate Logic TwoContemporary Logic Design TwoLevel Logic Gate Logic Two
Logic Gates Logic Gates A logic gate isLogic Gates Logic Gates A logic gate is
Lecture 26 Gate delays MOS logic Today GateLecture 26 Gate delays MOS logic Today Gate
LOGIC GATE TIMING DIAGRAM 1 And gate timingLOGIC GATE TIMING DIAGRAM 1 And gate timing
LOGIC GATES 1 AND Gate the AND gateLOGIC GATES 1 AND Gate the AND gate
Combinational Logic Other Gate Types Gate classifications PrimitiveCombinational Logic Other Gate Types Gate classifications Primitive
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Logic and Logic Programming Logic Propositional Logic FirstLogic and Logic Programming Logic Propositional Logic First
Logic Introduction to Logic What is logic LogicLogic Introduction to Logic What is logic Logic
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GATE Is Opening For Your Satisfaction GATE DuringGATE Is Opening For Your Satisfaction GATE During
Controlled NOT Toffoli Gate The Toffoli Gate TheControlled NOT Toffoli Gate The Toffoli Gate The