32 BIT PARALLEL LOAD REGISTER WITH CLOCK GATING

32 BIT PARALLEL LOAD REGISTER WITH CLOCK GATING PRARDIVA MANGILIPALLY ELEC 6270

OUTLINE: Objective Basic idea Basic gating circuit Modified clock gating circuit Design platform Results Conclusion

OBJECTIVE: To measure the average power for a 32 bit parallel load register with and without clock gating. To compare the results for the same. To study the effect of clock gating on power consumption for a 32 bit parallel load register.

CLOCK GATING: Clock gating is one of the power saving techniques in which additional logic is added to a circuit to prune the clock tree , thus disabling portions of circuitry so that flipflops do not change state. As a result switching power goes to zero.

MODIFIED CLOCK GATING CIRCUIT:

Design platform: Latchfree clock gating circuit Tools used: Modelsim, leonardo, Design Architect, Eldo Technology: tsmc 018 Clock frequency: 50 MHz Operating voltage: 1. 8 V

Pattern: 0000000 Without clock gating Average power: = 242. 6818 U W With clock gating Average power: 42. 8374 U W

Pattern: 11111 Without clock gating Average power: 244. 0567 UW With clock gating Average power: 27. 4138 UW

Pattern: 101010 Without clockgating Average power: 457. 2622 u. W With clock gating Average power: 628. 8430 U W

PATTERN: 1011 WITHOUT CLOCKGATING: AVERAGE POWER: 357. 8213 UW WITH CLOCK GATING AVERAGE POWER: 337. 1065 UW

PATTERN: 0100 WITHOUT CLOCKGATING AVERAGE POWER: 355. 11064 UW WITH CLOCKGATING AVERAGE POWER: 331. 2031 UW

PATTERN: 1101 WITHOUT CLOCKGATING: AVERAGE POWER: 352. 7703 UW WITH CLOCKGATING: AVERAGE POWER: 324. 1347 UW

PATTERN: 0010 WITHOUT CLOCKGATING AVERAGE POWER: 344. 7696 UW WITH CLOCKGATING AVERAGE POWER: 337. 4078 UW

INPUT 12: 00000010101000000000 WITHOUT CLOCK GATING: AVERAGE POWER: 288. 4402 UW WITH CLOCK GATING: AVERAGE POWER: 165. 1852 UW

INPUT 12: 11111010101111111111111111 WITHOUT CLOCKGATING: AVERAGE POWER: 289. 1212 UW WITH CLOCKGATING: AVERAGE POWER: 146. 8568 UW

Power Reductions: Without clock gating With clock gating TRANSITION DENSITY EXPECTED POWER (UW) OBSERVED POWER (UW) POWER REDUCTION (%) 0. 0000 244. 0512 244. 0567 68. 7008 27. 4138 88. 77 0. 0004 242. 6944 242. 6818 70. 1134 42. 8374 82. 35 0. 1000 262. 4961 289. 1212 182. 0272 146. 8568 49. 21 0. 1024 289. 1168 288. 4402 170. 3126 165. 1852 42. 73 0. 2500 357. 7568 357. 8213 340. 1931 337. 1065 5. 51 0. 5000 457. 1456 457. 2622 655. 6832 628. 840 -37. 5

CONCLUSIONS: Clock gating technique effectively reduces dynamic power in most of the cases. However, it increases power when there are transitions in every clock cycle. This increase is due to the extra power consumed by the ex-nor and nor gates in the clock gating circuit which account to about 58% increase in total hardware. If this increase in hardware could be reduced then the power savings can be increased even in the worst case which calls for the implementation of a different clock gating circuit or the usage of low power ex-or’s discussed in the class.

REFERENCES: Class lecture slides at http: //www. eng. auburn. edu/~vagrawal/ COURSE/ E 6270_Spr 09/course. html Frank Emnett and Mark Biegel, Power Reduction Through RTL Clock Gating, SNUG 2000(This paper discusses a method to avoid premature truncation of the clock).

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