307 2019 12 13 Designing Dynamic and Static
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ΗΜΥ 307 ΨΗΦΙΑΚΑ ΟΛΟΚΛΗΡΩΜΕΝΑ ΚΥΚΛΩΜΑΤΑ Εαρινό Εξάμηνο 2019 ΔΙΑΛΕΞΕΙΣ 12 -13: Designing Dynamic and Static CMOS Sequential Circuits ΧΑΡΗΣ ΘΕΟΧΑΡΙΔΗΣ (ttheocharides@ucy. ac. cy) (ack: Prof. Mary Jane Irwin and Vijay Narayanan) [Προσαρμογή από “Rabaey’s Digital Integrated Circuits, © 2002, J. Rabaey et al. ”]
Review: How to Choose a Logic Style l Must consider ease of design, robustness (noise immunity), area, speed, power, system clocking requirements, fan-out, functionality, ease of testing 4 -input NAND Style # Trans Comp Static 8 CPL* 12 + 2 domino 6+2 DCVSL* 10 Ease 1 2 4 3 Ratioed? Delay Power no 3 1 no 4 3 no 2 2 + clk yes 1 4 * Dual Rail q Current trend is towards an increased use of complementary static CMOS: design support through DA tools, robust, more amenable to voltage scaling. q CPL – Complementary Pass-Transistor Logic q Dynamic Cascade Voltage Swing (Logic) ΗΜΥ 307 Δ 12 -13: Dynamic& Static CMOS Sequential Circuits. 2 © Θεοχαρίδης, ΗΜΥ, 2019
Sequential Logic – REVIEW Inputs Combinational Logic State Registers Current State Outputs Next State clock ΗΜΥ 307 Δ 12 -13: Dynamic& Static CMOS Sequential Circuits. 3 © Θεοχαρίδης, ΗΜΥ, 2019
Timing Metrics In Out clock tsu In time thold data stable time tc-q Out D Q output stable time ΗΜΥ 307 Δ 12 -13: Dynamic& Static CMOS Sequential Circuits. 4 © Θεοχαρίδης, ΗΜΥ, 2019
System Timing Constraints Combinational Logic Current State Registers Inputs Outputs Next State T (clock period) clock tcdreg + tcdlogic thold ΗΜΥ 307 Δ 12 -13: Dynamic& Static CMOS Sequential Circuits. 5 T tc-q + tplogic + tsu © Θεοχαρίδης, ΗΜΥ, 2019
Static vs Dynamic Storage l Static storage ¤ ¤ ¤ preserve state as long as the power is on have positive feedback (regeneration) with an internal connection between the output and the input useful when updates are infrequent (clock gating) l Dynamic storage ¤ ¤ store state on parasitic capacitors only hold state for short periods of time (milliseconds to nanoseconds) require periodic refresh usually simpler, so higher speed and lower power ΗΜΥ 307 Δ 12 -13: Dynamic& Static CMOS Sequential Circuits. 6 © Θεοχαρίδης, ΗΜΥ, 2019
Latches vs Flipflops l Latches ¤ ¤ level sensitive circuit that passes inputs to Q when the clock is high (or low) - transparent mode input sampled on the falling edge of the clock is held stable when clock is low (or high) - hold mode l Flipflops (edge-triggered) ¤ edge sensitive circuits that sample the inputs on a clock transition ¢ ¢ ¤ positive edge-triggered: 0 1 negative edge-triggered: 1 0 built using latches (e. g. , master-slave flipflops) ΗΜΥ 307 Δ 12 -13: Dynamic& Static CMOS Sequential Circuits. 7 © Θεοχαρίδης, ΗΜΥ, 2019
Review: The Regenerative Property Vi 1 Vo 1 Vi 2 Vo 2 Vi 2 = Vo 1 cascaded inverters A C B If the gain in the transient region is larger than 1, only A and B are stable operation points. C is a metastable operation point. Vi 1 = Vo 2 ΗΜΥ 307 Δ 12 -13: Dynamic& Static CMOS Sequential Circuits. 8 © Θεοχαρίδης, ΗΜΥ, 2019
Bistable Circuits l The cross-coupling of two inverters results in a bistable circuit (a circuit with two stable states) q q Vi 1 Vi 2 Have to be able to change the stored value by making A (or B) temporarily unstable by increasing the loop gain to a value larger than 1 l done by applying a trigger pulse at Vi 1 or Vi 2 l the width of the trigger pulse need be only a little larger than the total propagation delay around the loop circuit (twice the delay of an inverter) Two approaches used l l cutting the feedback loop (mux based latch) overpowering the feedback loop (as used in SRAMs) ΗΜΥ 307 Δ 12 -13: Dynamic& Static CMOS Sequential Circuits. 9 © Θεοχαρίδης, ΗΜΥ, 2019
Review (from ECE 210): SR Latch S R !Q Q ΗΜΥ 307 Δ 12 -13: Dynamic& Static CMOS Sequential Circuits. 10 S R Q !Q 0 0 Q !Q memory 1 0 set 0 1 reset 1 1 0 0 disallowed © Θεοχαρίδης, ΗΜΥ, 2019
Review (from CSE 210): Clocked D Latch D Q D D Latch !Q Q clock transparent mode clock hold mode ΗΜΥ 307 Δ 12 -13: Dynamic& Static CMOS Sequential Circuits. 11 © Θεοχαρίδης, ΗΜΥ, 2019
MUX Based Latches q Change the stored value by cutting the feedback loop feedback 1 0 Q D 0 clk Q D 1 clk Negative Latch Positive Latch Q = clk & Q | !clk & D Q = !clk & Q | clk & D transparent when the clock is low transparent when the clock is high ΗΜΥ 307 Δ 12 -13: Dynamic& Static CMOS Sequential Circuits. 12 © Θεοχαρίδης, ΗΜΥ, 2019
TG MUX Based Latch Implementation clk Q !clk input sampled (transparent mode) D D D Latch clk Q clk ΗΜΥ 307 Δ 12 -13: Dynamic& Static CMOS Sequential Circuits. 13 !clk feedback (hold mode) © Θεοχαρίδης, ΗΜΥ, 2019
PT MUX Based Latch Implementation clk !Q Q D input sampled (transparent mode) !clk Reduced clock load, but threshold drop at output of pass transistors so reduced noise margins and performance q ΗΜΥ 307 Δ 12 -13: Dynamic& Static CMOS Sequential Circuits. 14 clk !clk feedback (hold mode) © Θεοχαρίδης, ΗΜΥ, 2019
Latch Race Problem Combinational Logic B’ State Registers B B clk Which value of B is stored? clk Two-sided clock constraint T tc-q + tplogic + tsu Thigh tc-q + tcdlogic ΗΜΥ 307 Δ 12 -13: Dynamic& Static CMOS Sequential Circuits. 15 © Θεοχαρίδης, ΗΜΥ, 2019
D 0 1 D QM 1 clk Master clk = 0 transparent clk = 0 1 hold Q clock Q 0 D FF Master Slave Based ET Flipflop clk Slave D hold QM transparent Q ET – Edge Triggered ΗΜΥ 307 Δ 12 -13: Dynamic& Static CMOS Sequential Circuits. 16 © Θεοχαρίδης, ΗΜΥ, 2019
MS ET Implementation Slave Master D I 2 T 2 I 1 T 1 I 3 I 5 T 4 I 4 T 3 I 6 Q QM clk master transparent slave hold clk master hold slave transparent !clk ΗΜΥ 307 Δ 12 -13: Dynamic& Static CMOS Sequential Circuits. 18 © Θεοχαρίδης, ΗΜΥ, 2019
MS ET Timing Properties l Assume propagation delays are tpd_inv and tpd_tx, that the contamination delay is 0, and that the inverter delay to derive !clk is 0 l Set-up time - time before rising edge of clk that D must be valid 3 * tpd_inv + tpd_tx l Propagation delay - time for QM to reach Q tpd_inv + tpd_tx l Hold time - time D must be stable after rising edge of clk zero ΗΜΥ 307 Δ 12 -13: Dynamic& Static CMOS Sequential Circuits. 20 © Θεοχαρίδης, ΗΜΥ, 2019
More Precise Setup Time ΗΜΥ 307 Δ 12 -13: Dynamic& Static CMOS Sequential Circuits. 21 © Θεοχαρίδης, ΗΜΥ, 2019
Setup/Hold Time Illustrations Circuit before clock arrival (Setup-1 case) ΗΜΥ 307 Δ 12 -13: Dynamic& Static CMOS Sequential Circuits. 22 © Θεοχαρίδης, ΗΜΥ, 2019
Setup/Hold Time Illustrations Circuit before clock arrival (Setup-1 case) ΗΜΥ 307 Δ 12 -13: Dynamic& Static CMOS Sequential Circuits. 23 © Θεοχαρίδης, ΗΜΥ, 2019
Setup/Hold Time Illustrations Circuit before clock arrival (Setup-1 case) ΗΜΥ 307 Δ 12 -13: Dynamic& Static CMOS Sequential Circuits. 24 © Θεοχαρίδης, ΗΜΥ, 2019
Setup/Hold Time Illustrations Circuit before clock arrival (Setup-1 case) ΗΜΥ 307 Δ 12 -13: Dynamic& Static CMOS Sequential Circuits. 25 © Θεοχαρίδης, ΗΜΥ, 2019
Setup/Hold Time Illustrations Circuit before clock arrival (Setup-1 case) ΗΜΥ 307 Δ 12 -13: Dynamic& Static CMOS Sequential Circuits. 26 © Θεοχαρίδης, ΗΜΥ, 2019
Setup/Hold Time Illustrations Hold-1 case 0 ΗΜΥ 307 Δ 12 -13: Dynamic& Static CMOS Sequential Circuits. 27 © Θεοχαρίδης, ΗΜΥ, 2019
Setup/Hold Time Illustrations Hold-1 case 0 ΗΜΥ 307 Δ 12 -13: Dynamic& Static CMOS Sequential Circuits. 28 © Θεοχαρίδης, ΗΜΥ, 2019
Setup/Hold Time Illustrations Hold-1 case 0 ΗΜΥ 307 Δ 12 -13: Dynamic& Static CMOS Sequential Circuits. 29 © Θεοχαρίδης, ΗΜΥ, 2019
Setup/Hold Time Illustrations Hold-1 case 0 ΗΜΥ 307 Δ 12 -13: Dynamic& Static CMOS Sequential Circuits. 30 © Θεοχαρίδης, ΗΜΥ, 2019
Setup/Hold Time Illustrations Hold-1 case 0 ΗΜΥ 307 Δ 12 -13: Dynamic& Static CMOS Sequential Circuits. 31 © Θεοχαρίδης, ΗΜΥ, 2019
Set-up Time Simulation Q Volts QM D tsetup = 0. 21 ns clk I 2 out works correctly Time (ns) ΗΜΥ 307 Δ 12 -13: Dynamic& Static CMOS Sequential Circuits. 32 © Θεοχαρίδης, ΗΜΥ, 2019
Set-up Time Simulation Q Volts I 2 out D tsetup = 0. 20 ns clk QM fails Time (ns) ΗΜΥ 307 Δ 12 -13: Dynamic& Static CMOS Sequential Circuits. 33 © Θεοχαρίδης, ΗΜΥ, 2019
Propagation Delay Simulation Volts tc-q(LH) = 160 psec tc-q(LH) tc-q(HL) = 180 psec Time (ns) ΗΜΥ 307 Δ 12 -13: Dynamic& Static CMOS Sequential Circuits. 34 © Θεοχαρίδης, ΗΜΥ, 2019
Reduced Load MS ET FF q Clock load per register is important since it directly impacts the power dissipation of the clock network. q Can reduce the clock load (at the cost of robustness) by making the circuit ratioed clk !clk I 1 D QM T 1 I 3 T 2 I 2 !clk Q I 4 clk reverse conduction l l to switch the state of the master, T 1 must be sized to overpower I 2 to avoid reverse conduction, I 4 must be weaker than I 1 ΗΜΥ 307 Δ 12 -13: Dynamic& Static CMOS Sequential Circuits. 35 © Θεοχαρίδης, ΗΜΥ, 2019
Non-Ideal Clocks clk !clk Ideal clocks Non-ideal clocks clock skew 1 -1 overlap 0 -0 overlap ΗΜΥ 307 Δ 12 -13: Dynamic& Static CMOS Sequential Circuits. 36 © Θεοχαρίδης, ΗΜΥ, 2019
Example of Clock Skew Problems X clk D P 1 A I 1 !clk P 3 I 2 B Q I 3 !Q I 4 P 2 P 4 !clk Race condition – direct path from D to Q during the short time when both clk and !clk are high (1 -1 overlap) Undefined state – both B and D are driving A when clk and !clk are both high Dynamic storage – when clk and !clk are both low (0 -0 overlap) ΗΜΥ 307 Δ 12 -13: Dynamic& Static CMOS Sequential Circuits. 37 © Θεοχαρίδης, ΗΜΥ, 2019
Pseudostatic Two-Phase ET FF X clk 1 D P 1 A I 1 clk 2 P 3 I 2 B Q I 3 I 4 P 2 P 4 clk 2 clk 1 !Q dynamic storage master transparent slave hold clk 1 tnon_overlap master hold slave transparent clk 2 ΗΜΥ 307 Δ 12 -13: Dynamic& Static CMOS Sequential Circuits. 38 © Θεοχαρίδης, ΗΜΥ, 2019
Two Phase Clock Generator A clk 1 B clk 2 clk A B clk 1 clk 2 ΗΜΥ 307 Δ 12 -13: Dynamic& Static CMOS Sequential Circuits. 39 © Θεοχαρίδης, ΗΜΥ, 2019
Power PC Flipflop !clk 1 D 0 1 !clk 1 0 Q 0 1 clk master transparent slave hold clk master hold slave transparent !clk ΗΜΥ 307 Δ 12 -13: Dynamic& Static CMOS Sequential Circuits. 41 © Θεοχαρίδης, ΗΜΥ, 2019
Ratioed CMOS Clocked SR Latch off on M 2 1 0 0 1 clk 0 S M 4 on off Q 1 0 !Q off->on M 8 M 6 M 1 on off M 5 off ΗΜΥ 307 Δ 12 -13: Dynamic& Static CMOS Sequential Circuits. 43 clk 0 1 M 3 off on M 7 on R 1 © Θεοχαρίδης, ΗΜΥ, 2019
Sizing Issues !Q (Volts) so W/L 5 and 6 > 3 W/L 5 and 6 W/L 2 and 4 = 1. 5 m/0. 25 m W/L 1 and 3 = 0. 5 m/0. 25 m ΗΜΥ 307 Δ 12 -13: Dynamic& Static CMOS Sequential Circuits. 44 © Θεοχαρίδης, ΗΜΥ, 2019
Transient Response Q & !Q (Volts) SET !Q tc-!Q Q tc-Q Time (ns) ΗΜΥ 307 Δ 12 -13: Dynamic& Static CMOS Sequential Circuits. 45 © Θεοχαρίδης, ΗΜΥ, 2019
6 Transistor CMOS SR Latch clk R S clk R M 5 M 2 !Q M 1 ΗΜΥ 307 Δ 12 -13: Dynamic& Static CMOS Sequential Circuits. 46 M 4 Q M 6 S M 3 © Θεοχαρίδης, ΗΜΥ, 2019
Review: Sequential Definitions l Static versus dynamic storage ¤ ¤ static uses a bistable element with feedback (regeneration) and thus preserves its state as long as the power is on static is preferred when updates are infrequent (clock gating) dynamic stores state on parasitic capacitors so only holds the state for a period of time (milliseconds) and requires periodic refresh dynamic is usually simpler (fewer transistors), higher speed, lower power l Latch versus flipflop ¤ latches are level sensitive with two modes: transparent - inputs are passed to Q and hold - output stable ¤ fliplflops are edge sensitive that only sample the inputs on a clock transition ΗΜΥ 307 Δ 12 -13: Dynamic& Static CMOS Sequential Circuits. 47 © Θεοχαρίδης, ΗΜΥ, 2019
Dynamic ET Flipflop master slave !clk D clk T 1 I 1 QM T 2 C 1 clk master transparent slave hold I 2 Q C 2 !clk tsu = tpd_tx thold = zero tc-q = 2 tpd_inv + tpd_tx clk !clk ΗΜΥ 307 Δ 12 -13: Dynamic& Static CMOS Sequential Circuits. 49 master hold slave transparent © Θεοχαρίδης, ΗΜΥ, 2019
Dynamic ET FF Race Conditions !clk D clk T 1 I 1 QM T 2 C 1 clk !clk ΗΜΥ 307 Δ 12 -13: Dynamic& Static CMOS Sequential Circuits. 50 I 2 Q C 2 !clk 0 -0 overlap race condition toverlap 0 -0 < t. T 1 +t. I 1 + t. T 2 1 -1 overlap race condition toverlap 1 -1 < thold © Θεοχαρίδης, ΗΜΥ, 2019
Dynamic Two-Phase ET FF clk 1 D clk 2 T 1 I 1 QM T 2 C 1 !clk 1 I 2 Q C 2 !clk 2 master transparent slave hold clk 1 tnon_overlap clk 2 master hold slave transparent ΗΜΥ 307 Δ 12 -13: Dynamic& Static CMOS Sequential Circuits. 51 © Θεοχαρίδης, ΗΜΥ, 2019
Pseudostatic Dynamic Latch l Robustness considerations limit the use of dynamic FF’s ¤ ¤ ¤ coupling between signal nets and internal storage nodes can inject significant noise and destroy the FF state leakage currents cause state to leak away with time internal dynamic nodes don’t track fluctuations in VDD that reduces noise margins l A simple fix is to make the circuit pseudostatic !clk D clk q Add above logic added to all dynamic latches ΗΜΥ 307 Δ 12 -13: Dynamic& Static CMOS Sequential Circuits. 52 © Θεοχαρίδης, ΗΜΥ, 2019
C 2 MOS (Clocked CMOS) ET Flipflop q A clock-skew insensitive FF Master Slave M 2 clk off D !clk off Mon 4 Mon 3 M 1 master transparent slave hold M 6 QM C 1 !clk on on Moff 8 Q Moff 7 C 2 M 5 clk !clk ΗΜΥ 307 Δ 12 -13: Dynamic& Static CMOS Sequential Circuits. 54 master hold slave transparent © Θεοχαρίδης, ΗΜΥ, 2019
C 2 MOS FF 0 -0 Overlap Case q Clock-skew insensitive as long as the rise and fall times of the clock edges are sufficiently small M 2 0 M 6 M 4 0 QM D M 8 Q C 1 C 2 M 1 M 5 clk !clk ΗΜΥ 307 Δ 12 -13: Dynamic& Static CMOS Sequential Circuits. 55 © Θεοχαρίδης, ΗΜΥ, 2019
C 2 MOS FF 1 -1 Overlap Case M 2 M 6 QM D 1 M 3 Q C 1 1 M 7 C 2 M 5 clk !clk 1 -1 overlap constraint toverlap 1 -1 < thold ΗΜΥ 307 Δ 12 -13: Dynamic& Static CMOS Sequential Circuits. 56 © Θεοχαρίδης, ΗΜΥ, 2019
C 2 MOS Transient Response For a 0. 1 ns clock QM(3) Volts Q(3) Q(0. 1) clk(3) For a 3 ns clock (race condition exists) Time (nsec) ΗΜΥ 307 Δ 12 -13: Dynamic& Static CMOS Sequential Circuits. 57 © Θεοχαρίδης, ΗΜΥ, 2019
True Single Phase Clocked (TSPC) Latches Negative Latch In clk Positive Latch clk Q hold when clk = 1 transparent when clk = 0 ΗΜΥ 307 Δ 12 -13: Dynamic& Static CMOS Sequential Circuits. 61 In Q clk transparent when clk = 1 hold when clk = 0 © Θεοχαρίδης, ΗΜΥ, 2019
TSPC ET FF Master D clk on off clk Slave on off QM master transparent slave hold clk ΗΜΥ 307 Δ 12 -13: Dynamic& Static CMOS Sequential Circuits. 64 on clk off clk on Q off master hold slave transparent © Θεοχαρίδης, ΗΜΥ, 2019
Simplified TSPC ET FF M 3 D clk off Mon 6 clk Mon off 2 X !D M 5 M 1 clk on Moff 4 M 9 QM 1 D clk off on M 8 Q D M 7 master transparent slave hold clk ΗΜΥ 307 Δ 12 -13: Dynamic& Static CMOS Sequential Circuits. 66 master hold slave transparent © Θεοχαρίδης, ΗΜΥ, 2019
Sizing Issues in Simplified TSPC ET FF clk !Qmod Volts !Qorig Qmod Transistor sizing Original width M 4, M 5 = 0. 5 m M 7, M 8 = 2 m Modified width M 4, M 5 = 1 m M 7, M 8 = 1 m Time (nsec) ΗΜΥ 307 Δ 12 -13: Dynamic& Static CMOS Sequential Circuits. 67 © Θεοχαρίδης, ΗΜΥ, 2019
Split-Output TSPC Latches Negative Latch Positive Latch Q In clk A transparent when clk = 1 hold when clk = 0 When In = 0, A = VDD - VTn ΗΜΥ 307 Δ 12 -13: Dynamic& Static CMOS Sequential Circuits. 68 A In clk Q hold when clk = 1 transparent when clk = 0 When In = 1, A = | VTp | © Θεοχαρίδης, ΗΜΥ, 2019
Split-Output TSPC ET FF D clk QM Q clk ΗΜΥ 307 Δ 12 -13: Dynamic& Static CMOS Sequential Circuits. 69 © Θεοχαρίδης, ΗΜΥ, 2019
Pulsed FF (AMD-K 6) q Pulse registers - a short pulse (glitch clock) is generated locally from the rising (or falling) edge of the system clock and is used as the clock input to the flipflop l race conditions are avoided by keeping the transparent mode time very short (during the pulse only) l advantage is reduced clock load; disadvantage is substantial increase in verification complexity OFF clk 0 1 P 1 ON X Vdd M 3 OFF ON 1/0 D 1 1 M 2 ON/ P 2 0 OFF 1 0 ΗΜΥ 307 Δ 12 -13: Dynamic& Static CMOS Sequential Circuits. 70 M 1 ON ON !clkd OFF 0/Vdd ON/OFF P 3 Q 1/0 M 6 OFF ON M 5 M 4 © Θεοχαρίδης, ΗΜΥ, 2019
Sense Amp FF (Strong. Arm SA 100) q Sense amplifier (circuits that accept small swing input signals and amplify them to full rail-to-rail signals) flipflops l advantages are reduced clock load and that it can be used as a receiver for reduced swing differential buses 0 D 1 1 M 2 0 M 5 1 M 9 M 7 Q M 1 M 4 1 !Q M 3 M 6 0 clk ΗΜΥ 307 Δ 12 -13: Dynamic& Static CMOS Sequential Circuits. 71 1 1 M 8 M 10 0 1 © Θεοχαρίδης, ΗΜΥ, 2019
Flipflop Comparison Chart Name Type #clk ld #tr tset-up thold tp. FF Mux Static 8 (clk-!clk) 20 3 tpinv+tptx 0 tpinv+tptx Power. PC Static 8 (clk-!clk) 16 2 -phase Ps-Static 8 (clk 1 -clk 2) 16 T-gate Dynamic 4 (clk-!clk) 8 tptx to 1 -1 2 tpinv+tptx C 2 MOS Dynamic 4 (clk-!clk) 8 TSPC Dynamic 4 (clk) 11 tpinv 3 tpinv S-O TSPC Dynamic 2 (clk) 10 AMD K 6 Dynamic 5 (clk) 19 SA 100 Sense. Amp 3 (clk) 20 ΗΜΥ 307 Δ 12 -13: Dynamic& Static CMOS Sequential Circuits. 72 © Θεοχαρίδης, ΗΜΥ, 2019
Choosing a Clocking Strategy l Choosing the right clocking scheme affects the functionality, speed, and power of a circuit l Two-phase designs ¤ ¤ ¤ + robust and conceptually simple - need to generate and route two clock signals - have to design to accommodate possible skew between the two clock signals l Single phase designs ¤ ¤ + + + - only need to generate and route one clock signal supported by most automated design methodologies don’t have to worry about skew between the two clocks have to have guaranteed slopes on the clock edges ΗΜΥ 307 Δ 12 -13: Dynamic& Static CMOS Sequential Circuits. 73 © Θεοχαρίδης, ΗΜΥ, 2019