3 HDL 10Shift Register Extraction Shift Register ExtractionFPGA

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3. HDL代码参数设置 （10）移位寄存器提取方式（Shift Register Extraction） Shift Register Extraction参数仅对FPGA有效，用于指 定是否使用移位寄存器（Shift Register）宏单元。 （11）逻辑移位寄存器提取方式（Logical Shifter Extraction） Logical

3. HDL代码参数设置 （10）移位寄存器提取方式（Shift Register Extraction） Shift Register Extraction参数仅对FPGA有效，用于指 定是否使用移位寄存器（Shift Register）宏单元。 （11）逻辑移位寄存器提取方式（Logical Shifter Extraction） Logical Shifter Extraction参数仅对FPGA有效，用 于指定是否使用逻辑移位寄存器（Logical Shifter）宏单 元。

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