3 D Integrated Circuit Fabrication Technology for High

3 -D Integrated Circuit Fabrication Technology for High Density Electronics Vyshnavi Suntharalingam Brian Aull, Robert Berger, Jim Burns, Chenson Chen, Jeff Knecht, Chuck Stevenson, Brian Tyrrell, Keith Warner, Bruce Wheeler, Donna Yost, Craig Keast 12 th Workshop on Electronics for LHC and Future Experiments 15 th International Workshop on Vertex Detectors 25 -29 September 2006 *This work was sponsored by the Defense Advanced Research Projects Agency under Air Force contract #FA 8721 -05 -C 0002. Opinions, interpretations, conclusions, and recommendations are those of the authors and are not necessarily endorsed by the United States Government. MIT Lincoln Laboratory LECC-Vertex-2006 -1 VS 9/25/06

Motivation for 3 -D Circuit Technology • • 3 -D Circuit = Multi-layer (multi-tier) stacked circuit High Density Advantages Vertical – Reduced interconnect length Interconnections – – • Reduced chip size Reduced parasitics Reduced power Fabrication process optimized by tier function Applications – – – High bandwidth microprocessors Mixed material system integration Advanced focal planes Process Technology Optimized by Tier Bump/Optical Connection Sites Mixed Material System Integration Local computation and/or memory 100% fill-factor diodes LECC-Vertex-2006 -2 VS 9/25/06 MIT Lincoln Laboratory

Pad-Level “ 3 D Integration” Die Stacking Stacked-Die Wire Bonding Stacked Chip-Scale Packages 1 mm Chip. PAC, Inc. LECC-Vertex-2006 -3 VS 9/25/06 Tessera, Inc. In Production! MIT Lincoln Laboratory

Pixel-Level 3 -D Integration Cross Sections Through Two-Tier Imager SOI-CMOS (Tier 2) SEM cross section Photodiode (Tier 1) 8 m decorated Transistor CMOS Vias 3 D-Via Bond Interface Diode LECC-Vertex-2006 -4 VS 9/25/06 8 m Pixel 5 mm MIT Lincoln Laboratory

Outline • Advantages of Vertical Integration for Focal Planes – MIT-LL Demonstration of Three-tier ring oscillators • Fabrication Sequence • MIT Lincoln Laboratory Demonstrations – – • Two-tier backside-illuminated visible imager Three-tier laser radar focal plane Three-tier 3 -D IC Multiproject Run Two-tier bonding and interconnection to In. P detector material Summary LECC-Vertex-2006 -5 VS 9/25/06 MIT Lincoln Laboratory

Limitations – Standard Bulk CMOS APS Monolithic APS – MAPS • Pixel Layout Fill factor compromised – Photodetector and pixel transistors share same area • photodiode Low photoresponsivity OUT – Shallow junctions – High doping – Limited depletion depth RST VDD ROW • High leakage – LOCOS/STI, salicide – Transistor short channel effects • Substrate bounce and transient coupling effects VDD ROW OUT RST n+ p-well Field Oxide p+ n-Well p-epi p+ Substrate LECC-Vertex-2006 -6 VS 9/25/06 MIT Lincoln Laboratory

Advantages of Vertical Integration Addressing Conventional Monolithic APS 3 -D Pixel Light PD pixel PD 3 T pixel ROIC Processor Addressing A/D, CDS, … • • Pixel electronics and detectors share area Fill factor loss Co-optimized fabrication Control and support electronics placed outside of imaging area LECC-Vertex-2006 -7 VS 9/25/06 • • • 100% fill factor detector Fabrication optimized by layer function Local image processing – Power and noise management • Scalable to large-area focal planes MIT Lincoln Laboratory

Approaches to 3 D Integration (Photos Shown to Scale) Tier-1 3 D-Vias Tier-3 3 D-Vias Tier-2 10 m Tier-1 Tier-2 10 m Photo Courtesy of RTI Bump Bond used to flip-chip interconnect two circuit layers LECC-Vertex-2006 -8 VS 9/25/06 10 m Two-layer stack with insulated vias through thinned bulk Si Three-layer circuit using Lincoln’s SOI-based vias MIT Lincoln Laboratory

3 -Tier, 3 D-Integrated Ring Oscillator (DARPA 3 DL 1 Multiproject Run) • Functional 3 -tier, 3 D-integrated ring oscillator – Uses all three active transistor layers, 10 levels of metal and experimental stacked 3 D-vias – Demonstrates viability of 3 D integration process 3 D Ring Oscillator Cross-Sectional SEM Tier-3: FDSOI CMOS Layer 3 D Via Stacked 3 D Via 3 D Tier-2: FDSOI CMOS Layer Via Transistors 5 m Stage Delay (ps) Tier-1: FDSOI CMOS Layer 99 -Stage Ring Oscillator @1. 5 V Power Supply (V) LECC-Vertex-2006 -9 VS 9/25/06 MIT Lincoln Laboratory

Outline • • Advantages of Vertical Integration for Focal Planes Fabrication Sequence and Five Key Elements – – – • MIT Lincoln Laboratory Demonstrations – – – • Low dark current photodiodes Silicon on Insulator (SOI) circuits Low-temperature, wafer-scale oxide-to-oxide bond Precision overlay High-density vertical interconnection Three-tier ring oscillators Two-tier backside-illuminated visible imager Three-tier laser radar focal plane Three-tier 3 -D IC Multiproject Run Two-tier bonding and interconnection to In. P detector material Summary LECC-Vertex-2006 -10 VS 9/25/06 MIT Lincoln Laboratory

3 -D Circuit Integration Flow-1 • Fabricate circuits on SOI wafers – SOI wafers greatly simplify 3 D integration • 3 -D circuits of two or more active silicon layers can be assembled Wafer-1 can be either Bulk, SOI, or Compound Semiconductor Buried Oxide Wafer-1 Handle Silicon Buried Oxide Wafer-2 Handle Silicon Buried Oxide Wafer-3 LECC-Vertex-2006 -11 VS 9/25/06 Handle Silicon MIT Lincoln Laboratory

1. Low Dark Current Photodiodes • Photodiode independent of CMOS • High-resistivity substrates 90, 000 parallel diodes • Back-illumination process • Photodiode leakage <0. 2 n. A/cm 2 @ 25ºC • Similar results after 10, 000 diodes (same area) Single tier test structure w/guard ring Full thickness wafer 3 D-stacking LECC-Vertex-2006 -12 VS 9/25/06 MIT Lincoln Laboratory

2. Silicon-On-Insulator Circuits • 3. 3 -V, 350 -nm gate length, 50 nm Si fully depleted SOI CMOS Buried Oxide • Buried oxide Silicon Handle Wafer – Dielectric isolation – Reduced parasitic capacitances – Enhanced radiation performance – Essential wafer-thinning etch stop LECC-Vertex-2006 -13 VS 9/25/06 silicided poly gate contact silicon channel Buried Oxide Handle Wafer MIT Lincoln Laboratory

3 -D Circuit Stacking • Invert, align, and bond Tier 2 to Tier 1 Oxide-Oxide Wafer Bond SOI Handle Wafer CMOS High-Resistivity Bulk Wafer LECC-Vertex-2006 -14 VS 9/25/06 PD MIT Lincoln Laboratory

3. Low Temperature Oxide Layer-to-Layer Bonding IR Image • Deeply scaled 3 -D interconnect technology requires robust waferto-wafer bonding technology • MIT-LL low temperature oxide bonding process provides (low-temperature oxide-bonded wafer pair) – Thin and controllable bondline – Enables use of standard IC high aspect ratio contact etch and plug fill technologies 150 mm Bonded Wafer-Pair Cross Section ~475 o. C process – Allows for 3 -D interconnect to be sintered Tier-2 metal oxide bond interface – Standard, high reliability semiconductor material Tier-1 metal LECC-Vertex-2006 -15 VS 9/25/06 5 m MIT Lincoln Laboratory

4. Precision wafer-to-wafer overlay • Provide a wafer-to-wafer alignment accuracy compatible with a submicron 3 D Via • Tool based on modern IC wafer stepper technology • 0. 5 m 3 -sigma overlay demonstrated Control Interface Mapping microscope Low mag. microscope NIR microscopes Bottom wafer chuck Top wafer chuck 150 -mm dia. wafer Low mag. video 6 -axis PZT stage Control computer Pre-align plate Laser interferometer controlled XY stage Mapping video LECC-Vertex-2006 -16 VS 9/25/06 MIT Lincoln Laboratory

Repeatability Data MIT-LL Precision Aligner Total Percent of Die Measured (%) 40 x x xxxxx x x X Offset Data 30 Y Offset Data 150 -mm wafer-pair (measurement locations) 20 +/- 0. 25 m 10 0 -1. 0 -0. 5 0. 0 0. 5 1. 0 Deviation ( m) • Data from five repeated alignments of same wafer pair • Nine die measured per alignment LECC-Vertex-2006 -17 VS 9/25/06 MIT Lincoln Laboratory

3 D Via Layout Comparison (Based on MIT-LL 180 nm FDSOI CMOS rules) Previous capability With recently developed precision alignment system and via technology CMOS Inverter 3 D via 2. 0 m 3 D via landing pad 5. 5 m 3 D via landing pad 2. 0 m 3 D via ~1. 0 m Inter-metal via 0. 4 m LECC-Vertex-2006 -18 VS 9/25/06 MIT Lincoln Laboratory

3 -D Circuit Stacking • Remove handle silicon from Tier-2 CMOS High-Resistivity Bulk Wafer LECC-Vertex-2006 -19 VS 9/25/06 PD MIT Lincoln Laboratory

Inter-Tier Via Connections • • Pattern, etch, and fill 3 -D vias (Additional circuit tiers could be added) Concentric 3 -D Via CMOS High-Resistivity Bulk Wafer LECC-Vertex-2006 -20 VS 9/25/06 PD MIT Lincoln Laboratory

5. High Density, High Yield, Compact 3 D-Via • Leverages standard high-yield IC process technology for 3 D interconnection – High density plasma oxide etch of via hole – Chemical vapor deposition of tungsten plug – Chemical mechanical planarization (CMP) to form damascene plug 3 D Via Cross-sections Tier-2 Metal Bond Interface CVD-W Plug Tier-1 Metal Circuit Tier-2 M 1 W 3 D-Via M 2 “Donut” Metal M 3 Oxide Bond Decorated Bond Interface Tier-1 Landing Pad Circuit Tier-1 Silicon LECC-Vertex-2006 -21 VS 9/25/06 MIT Lincoln Laboratory

Thermal Cycle Effects on 3 D-Via Chains Thermal Cycle: 300 K/ 77 K/ 300 K 3 D-Via Chain Resistance vs # of 3 D Vias and Thermal Cycles 10000 Total Resistance (Ω) 9000 # of cycles 8000 1 Cycle 2 Cycles 3 Cycles 4 Cycles 5 Cycles 6 Cycles 7 Cycles 8 Cycles 9 Cycles 10 Cycles 7000 6000 5000 4000 3000 2000 1000 0 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 # of 3 D Vias in Series LECC-Vertex-2006 -22 VS 9/25/06 MIT Lincoln Laboratory

Back Metal-1 and Back Metal-2 • • Deposit and pattern Back Metal-1 Deposit and CMP ILD Deposit and pattern Back Metal-2 Sinter CMOS High-Resistivity Bulk Wafer LECC-Vertex-2006 -23 VS 9/25/06 PD MIT Lincoln Laboratory

Completed Back-Illuminated CMOS Imager • • Thin photodiode substrate to 50 m Epoxy bond to quartz CMOS PD Transparent Substrate Light LECC-Vertex-2006 -24 VS 9/25/06 MIT Lincoln Laboratory

Outline • • Advantages of Vertical Integration for Focal Planes Fabrication Sequence • MIT Lincoln Laboratory Demonstrations – – – • Three-tier ring oscillators Two-tier backside-illuminated visible imager Three-tier laser radar focal plane Three-tier 3 -D IC Multiproject Run Two-tier bonding and interconnection to In. P detector material Summary LECC-Vertex-2006 -25 VS 9/25/06 MIT Lincoln Laboratory

Four-Side Abuttable Goal • • 3 -D CMOS imagers tiled for large-area focal planes Foundry fabricated daughter chip bump bonded to non-imaging side pixel Foundry Chip Tile with Daughter Chip mechanical mockup LECC-Vertex-2006 -26 VS 9/25/06 Tiled Array 8 mm MIT Lincoln Laboratory

Four-Side Abuttable Vertically Integrated Imager • Silicon photodetector layer (Tier-1) – • • Four-side abuttable 1024 x 1024 array of 8 m x 8 m pixels Address and readout layer (Tier-2) – 3. 3 volt FDSOI CMOS layer Timing, control, and analog-to-digital electronics (Tier-3) – • Light MOSIS fabricated chip bump bonded to detector array Active-pixel architecture for radiation tolerance 3 D-Integrated Tier-1/Tier-2 wafer pair > 1 million 3 D interconnects per imager 150 mm LECC-Vertex-2006 -27 VS 9/25/06 4 x 4 Tiled Array (mock-up) MIT Lincoln Laboratory

Design Goals • Four-side abuttable Active Pixel Sensor • 1024 x 1024 array of 8 m x 8 m pixels • 3 -D interconnections per pixel • 3. 3 -V operating voltage • Full digital control and readout at 10 fps LECC-Vertex-2006 -28 VS 9/25/06 MIT Lincoln Laboratory

Completed 3 D-Stacked Imager Wafer and Die Layout 150 -mm wafer 1024 x 1024 p-reset + cap 1024 x 1024 n-reset p-reset + cap n-reset p-reset, cap, SOI diode Process Monitoring Devices and Circuits 8 m LECC-Vertex-2006 -29 VS 9/25/06 22 mm MIT Lincoln Laboratory

3 T Pixel Schematic and Layout 8 mm +PDBIAS 3 D-Via VDDA 3 -D Via 15 f. F RSTLVL ROW VPIX • VSS LECC-Vertex-2006 -30 VS 9/25/06 Design Variations – p. FET Reset with 15 f. F capacitor – n. FET Reset with no capacitor MIT Lincoln Laboratory

Sample Dark Background • • Raw image without fixed pattern noise suppression Dominant yield detractor is row/column drop-outs Four Analog Outputs Panel 1 Panel 2 Panel 3 Panel 4 Open 3 D-Vias LECC-Vertex-2006 -31 VS 9/25/06 MIT Lincoln Laboratory

Four-Side Abuttable Vertically Integrated Imaging Tile • Wafer-Scale 3 D circuit stacking technology – Silicon photodetector tier – SOI-CMOS address and readout tier Per-pixel 3 D interconnections – 1024 x 1024 array of 8 m x 8 m pixels – 100% fill factor – >1 million vertical interconnections per imager Front Illuminated LECC-Vertex-2006 -32 VS 9/25/06 Back Illuminated MIT Lincoln Laboratory Presented at 2005 ISSCC

Outline • • Advantages of Vertical Integration for Focal Planes Fabrication Sequence • MIT Lincoln Laboratory Demonstrations – – – • Three-tier ring oscillators Two-tier backside-illuminated visible imager Three-tier laser radar focal plane Three-tier 3 -D IC Multiproject Run Two-tier bonding and interconnection to In. P detector material Summary LECC-Vertex-2006 -33 VS 9/25/06 MIT Lincoln Laboratory

Three-Tier Laser Radar Focal Plane • Based on single-photon-sensitive Geiger -mode avalanche photodiodes – 64 x 64 demonstration circuit (scalable to large imager formats) – Pixel size reduction from 100 m to 30 m – Timing resolution reduction from 1 ns to 0. 1 ns – 100 x reduction in voxel volume VISA 3 D Stack Cross Section Tier-3: 1. 5 V FDSOI CMOS Tier-2: 3. 5 V FDSOI CMOS APD Tier-1: 30 V Avalanche Photodiode VISA APD Pixel Circuit (~250 transistors/pixel) Pseudorandom counter circuit Completed Backside -illuminated 3 -tier, 3 D Laser Radar wafer APD drive/sense circuit 150 mm LECC-Vertex-2006 -34 VS 9/25/06 Avalanche PD MIT Lincoln Laboratory

64 x 64 LADAR Focal Plane First Demonstration of 3 -Tier Focal Plane Pixels • Rudimentary ladar image of 28” long cone with 8 -in timing resolution – Timing circuit limited to only 9 -bits of its full 12 -bit range 1 mm Complete 3 -tier, back-illuminated 64 x 64 APD Laser Radar Orientation of cone image on focal plane LECC-Vertex-2006 -35 VS 9/25/06 Grayscale range image with superimposed contours False color range image MIT Lincoln Laboratory

Outline • • Advantages of Vertical Integration for Focal Planes Fabrication Sequence • MIT Lincoln Laboratory Demonstrations – – – • Three-tier ring oscillators Two-tier backside-illuminated visible imager Three-tier laser radar focal plane Three-tier 3 -D IC Multiproject Run Two-tier bonding and interconnection to In. P detector material Summary LECC-Vertex-2006 -36 VS 9/25/06 MIT Lincoln Laboratory

3 -D IC Multiproject Run Completed (Three 180 -nm, 1. 5 volt FDSOI CMOS Tiers) • MIT-LL 3 D circuit integration technology • Preliminary 3 D design kits developed • - Wafer photo of completed tier-1 Mentor Graphics – MIT-LL, Cadence – NCSU, Thermal Models – CFRDC Design guide release 11/04, fab start 6/05, 3 D-integration complete 3/06 Concepts being explored in run: 150 -mm-diameter wafer 3 DL 1 Participants (Industry, Universities, Laboratories) LECC-Vertex-2006 -37 VS 9/25/06 MIT Lincoln Laboratory

3 D Technology Improvements (DARPA 3 DL 1 Multiproject Run) • 3 D technology enhancements successfully demonstrated in 3 DL 1 Run – Stacked 3 D-vias for electrical and thermal interconnect – 2 X reduction in 3 D-via size – Improved tier-to-tier overlay Stack 3 D-vias demonstrated High-Yield on >5000 -link Scaled 3 D-via Chains 5 m Scaled Conventional ~0. 5 m 3 s Tier-to-Tier Registration >95% yield on 4800 link chains Stacked 3 D-via resistance ~1 W Can be used as thermal vias 99 -Stage Ring Oscillator @1. 5 V 5 m LECC-Vertex-2006 -38 VS 9/25/06 MIT Lincoln Laboratory

Silicon to In. P Wafer Bonding • • Successful demonstration of 3 D-bonding of SOI CMOS circuit layer to In. P handle wafer Enables extension of 3 Dintegration technology to higher density, longer wavelength focal plane detectors – Tight pixel-pitch IR focal planes and APD arrays – In. Ga. As. P (1. 06 - m), In. Ga. As (1. 55 - m) Oxide-bonded circuit layer transferred from silicon wafer 150 -mm-diameter In. P Wafer LECC-Vertex-2006 -39 VS 9/25/06 MIT Lincoln Laboratory

Summary • MIT Lincoln Laboratory-developed 3 D circuit integration technology has been applied to advanced focal planes and three -tier computational circuits • Successful demonstrations: – Two-tier visible imager: 1024 x 1024 array of 8 m x 8 m pixels integrated to 100% fill factor photodiodes, backside illuminated – Three-tier ring oscillators in 180 -nm gate length technology – Three-tier laser radar focal plane: 64 x 64 array of Geiger-mode avalanche photodiodes with per-pixel timing and bias circuitry – Three-tier 3 -D IC Multiproject Run in 180 -nm gate length technology – Two-tier bonding and interconnection to SWIR-sensitive detector materials (In. P) LECC-Vertex-2006 -40 VS 9/25/06 MIT Lincoln Laboratory

Backups MIT Lincoln Laboratory LECC-Vertex-2006 -41 VS 9/25/06

1 1 Row Select Shift Register Integration Shift Register 1024 x 1024 Imager Array Architecture Column Select From 256 Four Outputs LECC-Vertex-2006 -42 VS 9/25/06 MIT Lincoln Laboratory

Bonded Two Wafer Imager Stack 150 -mm Diameter Wafer Pair LECC-Vertex-2006 -43 VS 9/25/06 MIT Lincoln Laboratory

Preliminary Tier-1 -2 3 D Imager Test Results • Electrical probe station preliminary imager test result using frontside illumination 1024 x 1024 Image from FIRST 3 D-Integrated Wafer Pair* – Final processing steps will result in unobstructed backside illuminated device SOI-CMOS circuit tier (Tier 2) Photodetector tier (Tier 1) *35 -mm slide image projected through CMOS-circuit-side of 3 D-integrated imager on chip test station Image acquired at 10 frames/sec (Background Subtracted, Pixel Yield > 99. 9%, 3. 8 M transistors) LECC-Vertex-2006 -44 VS 9/25/06 Presented at 2005 ISSCC MIT Lincoln Laboratory

Functional 3 D-Integrated, 3 -Tier Avalanche Photodiode Focal Plane Completed Pixel Cross-Sectional SEM • VISA laser radar focal plane based on single-photonsensitive Geiger-mode avalanche photodiodes – 64 x 64 format – 50 - m pixel size 3 D Via Transistors Tier-3: 1. 5 V SOI CMOS Layer 3 D Via Tier-2: 3. 5 V SOI CMOS Layer Tier-1: 30 V Back Illuminated APD Layer 10 m To-Scale Pixel Layout of Completed 3 -tier Laser Radar Focal Plane Tier-3 High-Speed Counter Tier-2 APD Drive/Sense Circuitry Tier-1 Avalanche Photodiode (APD) LECC-Vertex-2006 -45 VS 9/25/06 Presented at 2006 ISSCC ~250 transistors/pixel (50 mm x 50 mm) MIT Lincoln Laboratory

Cross-Section of 3 -Tier 3 D-integrated Circuit (DARPA 3 DL 1 Multiproject Run) 3 FDSOI CMOS Transistor Layers, 10 -levels of Metal Back Metal Tier-3: Transistor Layer Tier-3: 180 -nm, 1. 5 V FDSOI CMOS Stacked Vias 3 D-Via Metal Fill Oxide Bond Interface Tier-2: Transistor Layer 3 D-Via Tier-2: 180 -nm 1. 5 V FDSOI CMOS 3 D-Via 3 -Level Metal Oxide Bond Interface Tier-1: Transistor Layer Tier-1: 180 -nm, 1. 5 V FDSOI CMOS LECC-Vertex-2006 -46 VS 9/25/06 10 m MIT Lincoln Laboratory