3 D Circuit Integration Technology for Multiproject Fabrication

3 D Circuit Integration Technology for Multiproject Fabrication 7 April, 2000 James Burns, Andy Curtis, Paul Davis, Andy Loomis, Jim Reinold, Keith Warner, Peter Wyatt, Craig L. Keast, keast@LL. mit. edu MIT Lincoln Laboratory Lexington MA, 02173 3 -D Kickoff 1 CLK 4/7/00 MIT Lincoln Laboratory

Outline • Background – Motivation for 3 -D technology – Why Multiproject Fabrication? • Leveraging the FDSOI CMOS technology base • Current Status – Photodiode process development – 3 -D technology transfer – Wafer Aligner/Bonder purchase – 3 -D Via topologies • 3 -D Kickoff 2 CLK 4/7/00 Summary MIT Lincoln Laboratory

3 -D Circuit Technology • General Objective – Break away from the traditional 2 -D-constrained Moore’s Law scaling trends by developing and demonstrating a robust, high density, vertical chip-to-chip interconnection technology and making it available to the Do. D and research community through multiproject runs • Program Description (Joint effort with TREX Enterprises) – Develop enabling technologies for 3 -D integration Precision wafer-to-wafer overlay Low temperature wafer-to-wafer oxide bonding High density wafer-to-wafer electrical interconnects – Demonstrate the 3 -D technology by fabricating a high definition 3 -layer imaging module – Put in place infrastructure to allow for 3 -D multiproject fabrication 3 -D Kickoff 3 CLK 4/7/00 MIT Lincoln Laboratory

Motivation: 3 -D Circuit Technology Mixed Material System Integration High Bandwidth m-Processors Large Focal Planes Exploiting Different Process Technologies Advanced Imaging Technologies • Better circuit / interconnect ratio • “Unrestricted” vertical interconnections between layers • SOI CMOS Low digital system power: P=CV 2 f 3 D 3 -D Kickoff 4 CLK 4/7/00 MIT Lincoln Laboratory

3 -D Interconnect Demonstration Vehicle (Fully Parallel 64 x 64 APS Imager with A/D Conversion) A/D Converter Circuits fabricated in 1 -mm thick SOI CMOS Active Pixel Imaging Circuits fabricated in 10 -mm thick SOI CMOS Via Isolation SOI Buried Oxide Handle Wafer 10 -mm thick epi layer Plan View SOI Buried Oxide Handle Wafer Metal 1 Via Pad Isolation 6 mm 3 -D Kickoff 5 CLK 4/7/00 MIT Lincoln Laboratory

3 -D Process Flow Back Metal Interconnect Deep Via Cross Sectional SEM Deep Via Back Metal A/D Metal-1 Adhesive Imager Metal-1 Imager Metal-2 Imager Silicon 3 -D Kickoff 6 CLK 4/7/00 5 mm MIT Lincoln Laboratory

Developing 3 -D Multiproject Infrastructure • Transfer to, enhance and stabilize all aspects of the 3 -D fabrication process in Lincoln’s Microelectronics Laboratory – Initial program effort had different parts of the 3 -D fabrication process being performed at three different locations Starting circuit layer fabrication: MIT Lincoln Laboratory Wafer transfer and bonding: Kopin Corporation 3 -D via etch and metallization: Northeastern University • Demonstrate 3 -D circuit technology by fabricating a three-layer high definition imaging module SOI CMOS signal processing (layer 3) SOI CMOS A/D Converter (layer 2) Imaging Layer (layer 1) Thinned Bulk Si Wafer Backside illumination 3 -D Kickoff 7 CLK 4/7/00 MIT Lincoln Laboratory

Motivation: 3 -D Multiproject Fabrication • Mainstream silicon technology continues to focus on 2 -D centered technologies – This approach will probably continue for another ~10+ years unless something “revolutionary” happens – This is the low risk path, lots of inertia in the system • Maximizing the potential of 3 -D system architecture requires a new “thought process” – We need to get a group of talented individuals and/or teams thinking about the design/architecture issue as it relates to specialized Do. D and potential commercial system needs – This thinking needs to be focused in the context of a realizable 3 -D technology 3 -D Kickoff 8 CLK 4/7/00 MIT Lincoln Laboratory

Motivation: 3 -D Multiproject Fabrication (cont. ) • The 3 -D Multiproject Fabrication model provides the vehicle to explore the potential of 3 -D system integration across a broad research interest base – Putting in place a “user friendly” streamlined 3 -D integration technology built upon Aggressive low power, high performance SOI CMOS technology Robust oxide-based wafer bonding technology Precision wafer-to-wafer alignment technology – Provides the opportunity to explore mixed function (MEMS, CMOS, CCD, etc. ) and mixed material (Si, Si. Ge, Ga. As, etc. ) system integration • 3 -D Kickoff 9 CLK 4/7/00 Builds upon Lincoln Laboratory’s past Multiproject Run experience and core process technologies already in place and under development at the Laboratory MIT Lincoln Laboratory

Low Power, High Performance FDSOI CMOS Roadmap FY 98 FY 99 FY 00 FY 01 FY 02 MUMS 3 MUMS 2 Ship 6/14/99 Ship 7/15/98 Baseline 0. 25 mm SOI/CMOS MUMS 4 Start 1/1/00 0. 175 mm SOI/CMOS 0. 10 mm SOI CMOS Do. D/AS&T Merged CCD/CMOS MUMS 3. 5 LVA 1 LVA 2 Start 2/1/99 Start 4/1/00 Start 11/1/00 Do. D/R&T DARPA/ARMY Low Voltage Analog 3 -D Stacking Technology Honeywell/LM Damascene Waveguides 3 -D Layer Stacking RF MEMS Precision-MCM-D FDSOI CMOS In. Ga. As Detectors 3 -D Kickoff 10 CLK 4/7/00 Do. D/DTRA Rad Hard 0. 175 mm SOI/CMOS Integrated 3 -D Microsystems MIT Lincoln Laboratory

Advanced Photodiode Development • Current CMOS processes support diode fabrication but: Photodiode Process Simulation – Substrate doping too high for large depletion regions and high quantum efficiency • We are developing an enhanced photodiode process for the 3 -D effort based on existing Lincoln Laboratory photodiode technology 3 -D Kickoff 11 CLK 4/7/00 Microns – Leakage currents are too high for low noise photodiodes Microns MIT Lincoln Laboratory

3 -D Technology Transfer • Original program had process activities at: MIT-LL, NEU, and Kopin • All of these process activities are now being integrated in the MIT-LL Microelectronics Laboratory tool set 150 -mm Diameter Wafer Pair (Bonded and Thinned) – Wafer-to-wafer alignment and void-free bonding – 3 -D via etching – 3 -D via interconnect metallization 3 -D Kickoff 12 CLK 4/7/00 MIT Lincoln Laboratory

Wafer Aligner/Bonder Purchase • 3 -D Integration Program requires a precision wafer-towafer overlay and bonding system • We have researched the currently available commercial tools Wafer-to-Wafer Alignment (Bottom side referenced) – Barely satisfactory for the current 3 -D mutiproject demonstration effort – Clearly unsatisfactory for commercial 3 -D fabrication • Technology exists to make the necessary system but there is currently no market demanding the capabilities of such a tool 3 -D Kickoff 13 CLK 4/7/00 MIT Lincoln Laboratory

3 -D Via Topologies • Currently designing a mask set which will serve as the “workhorse” for developing the robust 3 -D interconnect technology – Supports 2 and 3 -layer stacking – Allows for the investigation of both topside-up and flipped wafer stacking techniques – Investigates multiple layer-to-layer via interconnect topologies W 3 – Designed for automated electrical characterization M 4 M 1 M 3 Shallow vias M 4 W 2 M 1 Deep vias M 3 M 2 M 1 Glue W 1 M 2 M 3 M 1 Si wafer 3 -D Kickoff 14 CLK 4/7/00 MIT Lincoln Laboratory

Summary • Developing the technology base necessary for demonstrating a robust 3 -D circuit interconnect technology – Original demonstration program was a team effort with Northeastern University and Kopin Corporation 64 x 64 imager with A/D conversion (>4, 000 3 -D interconnects) Sample Image – Follow-on multiproject effort is a collaboration between Lincoln Laboratory and a commercial technology transfer partner (TREX Enterprises) Transferring, while enhancing and streamlining, the 3 -D technology into the MIT Lincoln Laboratory “commercial” tool set – Program demonstrator is a three-layer, high definition (1280 x 1024) imaging module – Goal is to make 3 -D multiproject prototyping available in 2002 3 -D Kickoff 15 CLK 4/7/00 MIT Lincoln Laboratory