2012 EPICS Timing Workshop The Accelerator Timing System

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2012 EPICS Timing Workshop The Accelerator Timing System at SLAC: Experiences, Ideas & Future

2012 EPICS Timing Workshop The Accelerator Timing System at SLAC: Experiences, Ideas & Future Plans John Dusatko SLAC I&C Division / EE Department April 24, 2012 EPICS Timing Workshop 1 John Dusatko The SLAC Timing System

Introduction ►This talk will focus on the SLAC Timing System giving a bit of

Introduction ►This talk will focus on the SLAC Timing System giving a bit of history up to the development of the LCLS-I timing system and relate some of our experiences from that. ►This is followed by a description of our plans for LCLS-II and other systems ► Finally, I’ll present some ideas/wishlist for new features April 24, 2012 EPICS Timing Workshop 2 John Dusatko The SLAC Timing System

Background / History Legacy Timing System: Developed in the 1980 s for the SLC:

Background / History Legacy Timing System: Developed in the 1980 s for the SLC: CAMAC-based, generates triggers based on six AC mains-derived “Timeslot” signals Whole system triggered off of 360 Hz “Fiducial” (Generated from the three AC mains phases) Uses obsolete components *Still* in use (ran part of LCLS-I before upgrade and still running FACET) LCLS-I: Gave us the chance to develop a new timing system: Decision to use MRF Event System Had to co-exist with original SLC timing and was initially slaved to it (no longer following upgrade) This requirement affected some of our design decisions April 24, 2012 EPICS Timing Workshop 3 John Dusatko The SLAC Timing System

~ LCLS-I Timing/Event System Architecture Linac main drive line Linac Master Osc Low Level

~ LCLS-I Timing/Event System Architecture Linac main drive line Linac Master Osc Low Level RF FIDO Raw 360 Hz SLC MPG Master Pattern Generator LCLS Timeslot Trigger LCLS Master 476 Sync/Div MHz Oscillator 360 Hz 119 Mhz + FID Sq Wave on Coax F A N EPICS Network LCLS Timing System components are in RED P P m N D P E U T 2012 EPICS Timing Workshop TRD Tx TRD Rx fiber distribution TO: - Cav BPM - MPS BLM - MPS PIC - BCS LCLS-I Timing as originally implemented / Slaved to SLC Timing: formed event codes from SLC Timing Pattern (PNET) I E O V C R D E V TTL-NIM convert. SLC Trigs 4 TRD Rx 119 Mhz + FID Sq Wave on Coax 119 MHz P E I LCLS N SLC O events V E events C G T April 24, 2012 Fiber Cable PDU Digitizer LLRF BPMs Toroids Cameras Wire Scanner SLC klystrons John Dusatko The SLAC Timing System

~ LCLS-I Timing/Event System Architecture Linac main drive line FIDO Linac Master Osc Raw

~ LCLS-I Timing/Event System Architecture Linac main drive line FIDO Linac Master Osc Raw 360 Hz 60 Hz Timeslot 1 From MPS (Enet) PDU 119 Mhz + FID Sq Wave on Coax 119 MHz V C E M IRQ & LCLS P V T Timeslot events U G G F A N EPICS Network 2012 EPICS Timing Workshop TRD Tx 119 Mhz + FID Sq Wave on Coax Fiber distribution D E V TTL-NIM convert. 5 TO: - Cav BPM - MPS BLM - MPS PIC - BCS TRD Rx C E P V U R LCLS-I Timing De-Coupled from the SLC System. VMTG module provides Timeslot info and CPU forms event codes directly. The LCLS-II Timing System will look very similar to this April 24, 2012 TRD Rx LCLS Timeslot Trigger LCLS Master 476 Sync/Div MHz Oscillator 360 Hz Fiber Cable Digitizer LLRF BPMs Toroids Cameras Wire Scanner SLC klystrons John Dusatko The SLAC Timing System

LCLS-I Timing System Features & Comments: Has ~122 EVRs across 1. 5 KM of

LCLS-I Timing System Features & Comments: Has ~122 EVRs across 1. 5 KM of machine (not counting dev units) 85 PMC EVRs 37 VME EVRs (LLRF & BPM Subsystems) Due to distances, we had to use Single-Mode Fiber (replaced Multi-Mode SPFs with SM) Developed Separate TRD (Timing Reference Distribution) subsystem to provide 119 MHZ w/360 Hz phase-modulated fiducial to systems that didn’t need overhead of an EVR Developed Custom HW (Sync/Div, TRD, VMTG) in addition to MRF Event HW Extensive SW development effort (more so than the HW dev) Made some changes to MRF HW April 24, 2012 EPICS Timing Workshop 6 John Dusatko The SLAC Timing System

LCLS-II Timing System LCLS-II will timing will be very similar to LCLS-I Have its

LCLS-II Timing System LCLS-II will timing will be very similar to LCLS-I Have its own EVG LCLS-II will run on different timeslots than LCLS -I Both LCLS-I & -II timing systems will “know” about each other (via a synchronizing signal) Using u. TCA platform as well as VME April 24, 2012 EPICS Timing Workshop 7 John Dusatko The SLAC Timing System

LCLS-II Timing System Micro TCA Will be used in at least the BPM subsystem,

LCLS-II Timing System Micro TCA Will be used in at least the BPM subsystem, possibly LLRF as well Development effort underway Interim timing solution: PMC-EVR-200 on u. TCA adapter Planning on using/adapting Stockholm University u. TCA Timing Module (dev’d for XFEL) as final solution - Developed for XFEL - Distributes triggers & clock on u. TCA backplane - Double-wide (with RTM I/O) in development - Contains fiber phase stabilization mechanism April 24, 2012 EPICS Timing Workshop 8 John Dusatko The SLAC Timing System

Other SLAC Machines & Future Plans FACET: (1 st 2/3 rd of Linac) Uses

Other SLAC Machines & Future Plans FACET: (1 st 2/3 rd of Linac) Uses SLC timing for all Legacy Systems Uses Event System for all new subsystems (accelerator controls as well as experiments) XTA: X-Band Test Accelerator (stand-alone machine) Uses Event System for timing / coupled to SLC timing SPEAR-III: Considering Event System for booster upgrade PEP-X: Could/Would use Event System in some form Grand SLAC Timing System: Would tie together all related systems (don’t know what this would look like yet…) April 24, 2012 EPICS Timing Workshop 9 John Dusatko The SLAC Timing System

Timing Features Wishlist Desired Features: EVR Standby trigger capability FPGA Gateware mod to EVR

Timing Features Wishlist Desired Features: EVR Standby trigger capability FPGA Gateware mod to EVR to support stby triggers (completed on VME-EVR) Greater than 256 event codes Experiment support keeps asking for more ECs! Fanout Module Upgrade Added diagnostics for SFP status readout & single-level fanout ports Fiber Phase Stabilization SU u. TCA module has this feature Additional Diagnostics on EVG side Readout of parameters (RF power, phase, fiducial rate, etc. ) from Sync/Div chassis EVR SFP (optical xcvr) Diagnostics Readout for maintenance April 24, 2012 EPICS Timing Workshop 10 John Dusatko The SLAC Timing System