2 VLSI Basic Hiroaki Kunieda Dept of Communication

2. VLSI Basic Hiroaki Kunieda Dept. of Communication and Integrated Systems Tokyo Institute of Technology

VLSI Design with Verification Specification System Design System Verification Logic Design Logic Verification Layout Design Layout Verification RTL Netlist Mask Data Test Data

1. 3 Logic Gate

Logic Gate Class Static Logic CMOS Logic Pseudo NMOS Logic Dynamic Logic CMOS Domino Logic Characteristics Logic Delay Rise Time Fall Time Fan-in/ Fan-out Power Consumption

Ｌｏｇｉｃ Ｔｈｅｏｒｙ [Completeness] • Function {|}=NAND function: complete • 1: a|(a|a) = a|a’ = 1 • 0: {a|(a|a}|{a|(a|a)} = 1|1 = 0. • a’: a|a = a’. • ab: (a|b)|(a|b) = ab • a+b: (a|a)|(b|b) = a’|b’=a+b • NOR function: complete • AND and OR function: not complete [Irredundant] no literal can be removed. redundant Ab+ab’=a

Data sheet for 45 nm Process Parameter Symbols Data Oxide Thickness Tox 1. 3 (1. 7) nm Unit MOS Capacitor Cox 15. 67 f. F/um 2 Gate Capacitor (W=250 nm, L=25 nm) Cg 0. 160 f. F Sheet registance Rsheet 875 Ω/□ Relative permittivity εr 2. 3 Vacuum permittivity ε 0 8. 85418782 p. F/m NMOS On current（L=35 nm) Ion(n) 1360 u. A/um PMOS Off current (L=35 nm) Ion(p) 1070 u. A/um Off leak current (L=35 nm) Ioff 100 n. A/um

Data sheet for 45 nm Process Parameter Symbols Data Power Supply Voltage VDD 1. 0 V Gain factor K 7. 81 u. A/V 2 Threshold voltage Vth 0. 4 V Gate delay Tau 10 psec Unit on resistor (L=35 nm) Ro 220. 6 Ω-um Unit Capacitor (L=35 nm) Co 45. 3 f. F/um Wire R Rline 500 Ω/mm Wire C Cline 300 f. F/mm #layer for wire #layer 12

MOS n n n “MOS” : sandwich structure of Metal, Oxide, and Silicon (semiconductor substrate). The positive voltage on the polysilicon forms gate attracts the electron at the top of the channel. The threshold voltage (Vt) collects enough electrons at the channel boundary to form an inversion layer (p -> n). Field Oxide Gate Oxide

Transistor Parasitics n n Cg: gate capacitance = 0. 9 f. F/μm 2 (2 μprocess) Cgs/Cgd: source/drain overlap capacitance =Cox W (Cox: gate/bulk overlap capacitance)

A Simple Transistor Model Linear region Saturated region l l n. MOS transistor become on by applying high voltage to gate to provide current. p. MOS transistor becomes on by applying low voltage to gate to provide current

Static Complementary Gates VDD Pullup network (p. MOS) • output is connected to VDD Ro/W Co. W VSS Pulldown network (n. MOS) • Output is connected to VSS Pull up Pull down

Vin-Vout DC Characteristics VOH Noise Margin NML = VIL-VOL NMH = VOH-VIH VOL VIL

CMOS NAND & NOR Pullup network (p. MOS) • output is connected to VDD when ab=0. VDD VSS Pulldown network (n. MOS) • Output is connected to VSS when ab=1.

Relation between n. MOS and p. MOS Dual graph

And Or Inverter (AOI) gate (ab+c)’

Adders si =ai bi ci =(ai bi) ci = Pi ci ci+1=aici+bici+aibi=(ai bi)ci+aibi =Pici+Gi

1. 3 Gate Delay and Wire Delay

Gate Delay (delay model) Let’s suppose that Wp = 2 Wn which makes the same pull up and pull down current with ON-resistance of, Ro/W where Ro is the resistance per unit width. (ex. 200 Ωum） Load capacitance consisting of drain junction capacitance is corresponded by the area of the drain such as Co. W where Co is the capacitance per unit width (ex. 50 f. F/um) Input capacitance is also represented by Co. W L=35 nm=0. 035 um (45 nm)

Gate Delay Pull up current is represented by VDD/Ron(p). Pull down current is represented by VDD/Ron(n) Gate Delay (W=0. 35 um, L=0. 035 um) Co. W Ro/W = (Ro/W) x (Co. W) Ro/W = Ro Co Co. W = 200 Ωum ｘ 50 p. F/um Pull up Pull down = 10 psec Pull up/down currents are represented by ON resistance, which are reversely corresponded by the channel width W.

2 stage gates without load p. The first term represents the delay of the 1 st stage, where the output charge and the input charge of the 2 nd stage is pull up or down by the current driven by the 1 st gate. Both charge and current corresponds to the size or the channel width w. p. The second term represents the delay of the 2 nd stage. Without any load to the gates, the delay becomes identical to, which depends on the process. Delay = 1 st stage delay + 2 nd stage delay = (Ro/W 1) (Co. W 1+Co. W 2) + (Ro/W 2)(Co. W 2) = Ro. Co (2+W 2/W 1) = 10 psec x 3 = 30 psec

2 stage gates with load Load Capacitance is total sum of input capacitance Co. Wload Delay = 1 st stage delay + 2 nd stage delay = (Ro/W 1) (Co. W 1+Co. W 2) + (Ro/W 2)(Co. W 2+Co. Wload) = Ro. Co (2+W 2/W 1+Wload/W 2) Case 1. W 2=W 1, Load=10 W 1 Delay = 10 psec (2+1+10) = 130. 0 psec Case 2. W 2=3 W 1, Load=10 W 1 Delay = 10 psec (2+3+3. 33) =83. 3 psec

Wires Delay Elmore Delay Model Delta 1=r 1 x (C 1+---+Cn) =n ｔc Delta 2=r 2 x (C 2+----+Cn) =(n-1)ｔc Delta. N=rn x Cn =ｔc total=Delta 1+ ----- + Delta. N =[n(n+1)/2] ｔc

Wire Delay Rline=2. 0 Ω-um Cline=0. 3 f. F/um Ro=200 Ω*um Co= 50 f. F/um W 1=W 2=0. 35 u Line=2 N um Delay=(R 0/W 1) (Co. W 1+Co. W 2+Cline. Line) +(Rline. Line) (Co. W 2+(Cline/2)Line) =200 x （2 x 50 f + 2 x. N)+2 x (10 f+0. 5 N) = 50 nsec + 26*N nsec (line =2 x. N um) Delay = Ro/W 1 (Co. W 1+Co. W 2) =2. 5 K x 20 f. F =50. 0 nsec (line=0)

Wire Delay Rline=500 Ω/um Cline=300 f. F/um Ro=25 kΩ*um Co=0. 5 f. F/um W 1=W 2=0. 35 u Line=0. 5 um Delay=(R 0/W 1) (Co. W 1+Co. W 2+Cline. Line) +(Ro/W 1+Rline. Line) (Co. W 2+(Cline/2)Line) =50 K x （0. 5 f + 50 K x (0. 25+0. 125) = 37. 5 nsec + 18. 8 nsec =56. 3 nsec (line =0. 5 um) Delay = Ro/W 1 (Co. W 1+Co. W 2) =50 K x 0. 5 f. F =25 nsec (line=0)

1. 4 Flipflop and Memory

Switch Logic 0 transfer Logic 1 transfer

Latch Charge sharing: the stored data of A is connected to the latch’s output. Additional buffer may be required to drive output load.

Clocked Inverter n n tristate inverter produces restored output or Hi. Impedance Z Used as latch circuit

Latch

D Flip-flop Operation

Scan in DFF Functional Schematic of DFF with Scan 31 ACSEL Lab University of California, Davis

Memory Structure Read-Only Memory (ROM) Random Access Memory (RAM) Static RAM (SRAM) Dynamic RAM (DRAM)

Static RAM Cell • Read • Precharge bit and bit’ • Asert Select line • Write • Bit and bit’ lines are set to desired values. • Select is set to 1.

RAM Ｃｅｌｌ n Write n n set bit line Read n n Precharge firstly bit line Activate word line

1. 5 Data Path and Control Circuit

Data Path 1

Control Sequential Logic Circuit

Data Path 2 0 1 2 3 4 5 6 7 DA 1 DB 1 * DC 1 DA 2 DB 2 * DC 2 Load. A 1 0 0 0 Reg. A * DA 1 DA 2 Load. B 0 1 0 0 Reg. B * * DB 1 DB 2 Load. C 0 0 1 0 Reg. C * * * DC 1 DC 2 BUS During Clk=2, adder operation must be completed within 1 clock.

1. 6 Design and Verification