2 8 Address bits Data bits 00101011 10001111
2 × 8 Address bits × Data bits 00101011 10001111 10101011 01001000 00 01 10 11
3 × 8 Address bits × Data bits 00101011 10001111 10101011 01001000 000 001 010 011 100 101 110 111
4 × 8 Address bits × Data bits 00101011 10001111 10101011 01001000 0000 0001 0010 0011 0100 0101 0110 0111 00101011 10001111 10101011 01001000 1001 1010 1011 1100 1101 1110 1111
2 × 8 Address bits × Data bits 00101011 10001111 10101011 01001000 00 01 10 11
2 × 16 Address bits × Data bits 00101011 10001111 10101011 01001000 00 01 10 11
2 × 32 Address bits × Data bits 0010101100101011 1000111110001111 1010101110101011 0100100001001000 00 01 10 11
2 Address bits a b f g 00 22=4 0 1 Addresses 1 0 1 0 0 0 2 0 Bits per 0 Word 1 4 Words 4*2=8 Bits Stored
ab c 000 001 3 Address 0 1 0 bits 0 1 1 23=8 1 0 0 Addresses 1 0 1 110 111 f 0 1 0 0 0 1 1 1 g 0 0 0 1 1 2 Bits per Word 8*2=16 Bits Stored
ab c 000 001 3 Address 0 1 0 bits 0 1 1 23=8 1 0 0 Addresses 1 0 1 110 111 f 0 1 0 0 0 1 1 1 g 0 0 0 1 1 h 0 1 0 1 i 1 0 1 1 0 4 Bits per Word 8*4=32 Bits Stored
ab c 000 001 3 Address 0 1 0 bits 0 1 1 23=8 1 0 0 Addresses 1 0 1 110 111 f 0 1 0 0 0 1 1 1 g 0 0 0 1 1 h 0 1 0 1 i 1 0 1 1 0 j 1 1 1 1 0 k 0 0 1 1 0 1 l 0 1 0 0 1 1 1 0 m 0 8 0 Bits per Word 0 0 0 8*8=64 Bits 0 0 Stored 1
a 2 a 1 a 0 8× 8 ROM d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0
ROM Addressed Words PLA Addressed Words RAM Addressed Words
ROM Addressed Words Not Minimal PLA Addressed Words Minimal RAM Addressed Words Not Minimal
ROM Addressed Words Not Minimal Combinational Non-Volatile Program once PLA Addressed Words Minimal Combinational Non-Volatile Program once RAM Addressed Words Not Minimal Sequential Volatile Constantly rewritten
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