2 1 i Constraints Understanding Timing and Placement

2. 1 i Constraints Understanding Timing and Placement Constraints HDL and M 1. 5, 7/10/98 Slide 1

UCF User Constraints File XNF/EDIF netlist NGDBUILD Flatten Hierarchical Design. NGD MAP M 1 Design Flow Logical to Physical translation Group LUTs and FFs into CLBs Optional: Reports block delays . NCD . PCF PAR Layout of Physical Design Routes Physical Design TRCE Static Timing Estimates BITGEN Generates configuration file . NCD. BIT Timing & Constraints, 7/22/98 Slide 2

What Needs Constraining? w Internal clock speed for one or more clocks w I/O speed w Logic using multi-cycle clocks w Pin to Pin timing w Pin Locations & Logic Locations Clk & CE Speed I/O Speed X CLK Y D Q D I/O Speed Q Logic Locations Z<0: 9> Pin 2 Pin Speed Timing & Constraints, 7/22/98 Slide 3 1 Level of Logic 2 Levels of Logic OUT 1 OUT 2 Pin Locations

Types of constraints supported w Timing Constraints —Specify delay along logic paths —Allows both “quick and dirty” and “highly detailed” timing control w Location Constraints —Specify location of components on FPGA —Specify mapping constraints Timing & Constraints, 7/22/98 Slide 4 ST IN _ MY AP FM C AB M= N LK BC B ST IN 1 OP FL BL A M= KN BC 2 OP FL BL A M= KN

Where do Constraints go? w Timing constraints may be applied to a Schematic using the TIMESPEC symbol (FROM: TO’s) w They can be added to HDL source code if your compiler supports them w They can be input in a separate file called a. UCF (User Constraints File) w Some constraints must be placed in the PCF (Physical Constraints File). Normally, the PCF should be avoided by users. TIMESPEC Timing & Constraints, 7/22/98 Slide 5

Brief Review of Constraint Flow LOGICAL DOMAIN UCF User Constraints File XNF/EDIF netlist User netlist and logical constraints NGDBUILD DESIGN TRANSLATION MAP PHYSICAL DOMAIN . NCD PAR Timing & Constraints, 7/22/98 Slide 6 TRCE Mapped design and physical constraints . PCF EPIC NGDANNO DRC

Timing Constraints (I) Using PERIOD and OFFSET constraints HDL and M 1. 5, 7/10/98 Slide 7

Period Constraints PERIOD w w PERIOD is the duration of the clock and can be configured to have different duty cycles Derived clocks can be defined as a function of another clock (*, /) PERIOD is preferred over FROM: TO constraints; The tools will have a faster runtime. PERIOD should cover most of design. Period only covers from Sync. Elements to other Sync. Elements, like Flip flops to flip flops. Timing & Constraints, 7/22/98 Slide 8

The Period Constraint w Period : This constraint covers all timing paths which start and end at a FF, Latch or synchronous RAM which is clocked by the referenced net. (Every synchronous element is effectively identified by forward propagation. ) w It does not cover paths. LATCH to output pads, but does cover FLOP D Q input pads. D Q OUT 1 CLK G PERIOD=30 RAM OUT 2 Path controlled by PERIOD Forward propagation path w UCF Example: — Using “simple” method: NET A_CLK PERIOD=40 : LOW 15; duty cycle) — Using TIMEGROUP/TNMs NET A_CLK TNM = A_CLK_GRP; Timing & Constraints, 7/22/98 Slide 9 ……(LOW is optional; Specifies …. . . (make a group)

Period Path Tracing w PERIOD analyzes the following: — Synchronous element to synchronous element data path calculations — Automatically deals with inverted clock pins — Deals with non 50% clock duty cycles — Synchronous element to PAD, PAD to PAD, and PAD to Synchronous element NOT included w Clock Network to Clock Network uses Target Clock as Time Constraint Period#2 will control this path Period#1 Timing & Constraints, 7/22/98 Slide 10 Period#2

Period and Two-Phase Clocks w The allowed path delay will automatically be reduced if a two-phase clock is detected — If PERIOD does not have a “HIGH” or “LOW” keyword to define duty-cycle, then allowed path delay will be cut in half Single-Phase Maximum Two-Phase Maximum =================================== Timing constraint: NET "clock" PERIOD = 45 n. S HIGH 50. 000 % ; 2 items analyzed, 0 timing errors detected. Minimum period is 8. 586 ns. ----------------------------------Slack: 18. 207 ns path qneg_buf to qneg_buf relative to 22. 500 ns delay constraint (two-phase clock) Path qneg_buf to qneg_buf contains 2 levels of logic: Path starting from Comp: CLB_R 1 C 7. K (from clock_buf) To Delay type Delay(ns) Physical Resource Logical Resource(s) -------------------------CLB_R 1 C 7. XQ Tcko 1. 830 R qneg_buf CLB_R 1 C 7. C 2 net (fanout=2) 0. 543 R qpos_buf CLB_R 1 C 7. K Thh 1 ck 1. 920 R qneg_buf ------------------------Total (3. 750 ns logic, 0. 543 ns route) 4. 293 ns (to clock_buf) Timing & Constraints, 7/22/98 Slide 11 45 ns is the maximum allowed PERIOD declared in the UCF TRCE cut the spec in half (45 ns/2=22. 5 ns) for this path “Two-phase clock” is indicated here This indicates the magnitude of the path delay between flops. There is no “adjustment” to this figure. This indicates that the worst-case period for this ENTIRE spec is 8. 586 ns (4. 293 ns x 2). If there had been a single-phase path in this PERIOD spec that was 9 ns, it would have been reported as the worst-case value, if it were 8 ns, it would not. This is the remaining slack (45 ns/2 - 4. 293 ns = 18. 207 ns).

Period and RAM w PERIOD will trace THROUGH the Address pins of all RAM, and TO the D/WE pins of Sync RAM (THROUGH WE of Async) Sync RAM WE D WCLK ADDRESS ASync RAM WE ADDRESS Timing & Constraints, 7/22/98 Slide 12

Period Examples w By net — — NET CLK 50 PERIOD = 20 ns ; NET CLK 20 PERIOD = 50 HIGH 20 ; w By group: (See TNM/TIMEGRP Section for details) — — NET CLK 50 TNM = CLK 50_GRP ; NET CLK 25 TNM = CLK 25_GRP ; TIMESPEC TS_CLK_FULL = PERIOD CLK 50_GRP 20; TIMESPEC TS_CLK_HALF = PERIOD CLK 25_GRP TS_CLK_FULL * 2 ; (Note M 1. 5 - must use signal after global buffer for TNM groups) TNM=CLK 50_GRP BUFG Timing & Constraints, 7/22/98 Slide 13

I/O Timing: Offset w OFFSET allows the user to specify external data and clock relationships for the timing on paths to and from the I/Os. The software determines the internal requirements (OFFSET IN AFTER, OFFSET OUT BEFORE). w Optionally, OFFSET allows the user to specify the internal delay (OFFSET IN BEFORE, OFFSET OUT AFTER). w OFFSET was originally added to support Synopsys set_input_delay and set_output_delay constraints w For clocks using global resources, the clock delay is used in the equation w Note: The path from the pad to a FF in an IOB is not constrained by offset. This is considered a Timing & Constraints, 7/22/98 Slide 14

Specify I/O timing w OFFSET allows the user to specify EXTERNAL data and cloc relationships for the timing on paths to and from the IO’ w It enables the user to inform the system of external setup clock-to-out delays with respect to a clock. The system ca determine the internal timing requirements without the ne PADS: TO: FFS or FFS: TO: PADS constraints. Internal delays determined by the tools OFFSET OUT OFFSET IN d 2 d 3 d 4 d 1 DEV 1 CLK Timing & Constraints, 7/22/98 Slide 15 FPGA DEV 2

The OFFSET IN - ‘BEFORE’ constraint NET Din OFFSET = IN 20 n. S BEFORE CLK FPGA UPSTREAM DEVICE Din CLK This says, Data will be valid here, 20 n. S BEFORE the clock arriv In other words: “The Data to be registered in the FPGA will be available on the FPGA’s input Pad 20 ns BEFORE the clock pulse is seen by the FPGA’s clock pad. ” Therefore, the M 1 tools will calculate: Maximum_Allowable_Internal_P 2 S_Delay = OFFSET + internal_CLK_delay. Data registered in FPGA on this edge. 20 ns Data Out of DEV 1 on this edge. Valid Tbufg Internal delay Timing & Constraints, 7/22/98 Slide 16 Tsu. FF Valid The tools can automatically calculate and control internal data and clock delays to meet Tsu. FF Designer must ensure that T(clock_period) - 20 ns = ext-delay

The OFFSET IN - ‘AFTER’ constraint NET CLK PERIOD = 45 n. S; NET Din OFFSET = IN 16 n. S AFTER CLK; FPGA UPSTREAM DEVICE Din CLK This says, Data will be valid here, 16 n. S AFTER the clock arrive In other words: “The Data to be registered in the FPGA will be available on the FPGA’s input Pad 16 ns AFTER the clock pulse is seen by the Upstream Device. ” For the purposes of the OFFSET constraint syntax, assume no skew on CLK between the chips. A PERIOD constraint is required to indicate when the subsequent clock pulse will be seen by the FPGA to clock in the Data (Maximum_Allowable_Internal_P 2 S_Delay = PERIOD - OFFSET + internal_CLK_delay). 16 ns Data Out of DEV 1 on this edge. Timing & Constraints, 7/22/98 Slide 17 Valid Data registered in FPGA on this edge. For this example, the max. P 2 S delay would be calculated by M 1 as : 45 ns-16 ns+3 ns = 32 ns. (Assuming internal CLK delay is 3 ns. )

The OFFSET OUT - ‘AFTER’ constraint NET Din OFFSET = OUT 22 n. S AFTER CLK FPGA DOWNSTREAM DEVICE This says, Data will be valid here, 22 n. S AFTER the clock arrive In other words: “The Data to be registered in the Downstream Device will be available on the FPGA’s output Pad 22 ns AFTER the clock pulse is seen by the FPGA. ” (Maximum_Allowable_Internal_Dout_Delay = OFFSET - internal_CLK_delay). 22 ns Data Out of FPGA on this edge. Timing & Constraints, 7/22/98 Slide 18 Valid Data clocked into DEV 2 on this edge. Designer must ensure that T(clock_period) - 22 ns = ext-delay = sufficient time for external delays involved with meeting DEV 2 setup time.

The OFFSET OUT - ‘BEFORE’ constraint NET CLK PERIOD = 45 n. S; NET Din OFFSET = OUT 25 n. S BEFORE CLK; d 4 FPGA DEV 2 This says, Data will be valid here, 25 n. S BEFORE the clock arrives here!…. . In other words: “The Data to be registered in the Downstream Device will be available on the FPGA’s output Pad 25 ns BEFORE the clock pulse is seen by the Downstream Device. ” For the purposes of the OFFSET constraint syntax, assume no skew on CLK between the chips. A PERIOD constraint is required to indicate when the initial clock pulse was seen by the FPGA to clock out the Data (Maximum_Allowable_Internal_C 2 P_Delay = PERIOD - OFFSET - internal_CLK_delay). Data Out of FPGA on this edge. Timing & Constraints, 7/22/98 Slide 19 25 ns Valid Data Into DEV 2 on this edge. For this example, the max. C 2 P delay would be calculated by M 1 as : 45 ns-25 ns-3 ns = 17 ns. (Assuming internal CLK delay is 3 ns. )

OFFSET Constraints in 2. 1 i w Global: All inputs/outputs are offset relative to a clock. For example, OFFSET = IN 20 ns BEFORE clk 1 indicates that all inputs will have data present at the pad at least 20 ns before the triggering edge of clk 1 arrives at the pad. w Net-Specific: A specific input/output is offset relative to a clock. For example: NET DATA_IN OFFSET = IN 20 ns BEFORE clk 1 indicates that DATA_IN will have data present at the pad at least 20 ns before the triggering edge of clk 1 arrives at the pad. Timing & Constraints, 7/22/98 Slide 20

Clock Register Groups in OFFSET w Clock register time groups allows the user to define a specific set of registers to which an OFFSET constraint applies based on a clock edge. Consider the following example. NET CLK PERIOD = 45 n. S; OFFSET = IN 10 BEFORE CLK TIMEGRP AB; OFFSET = IN 20 BEFORE CLK TIMEGRP C; DATA A B C CLK You can define time groups for the registers A, B, and C, even though these registers have the same data and clock source. TIMEGRP AB = RISING FFS; TIMEGRP C = FALLING FFS; This allows the user to perform two different timing analysis for the registers. Timing & Constraints, 7/22/98 Slide 21

Data Path Groups in OFFSET w Data Path Groups allow the user to define a specific set of input pads to which an OFFSET constraint applies. Consider the following example. TIMEGRP DATA_GRP = PADS(DATA*); NET CLK PERIOD = 45 n. S; TIMEGRP DATA_GRP OFFSET = IN 10 BEFORE CLK; Data 1 A Data 2 Data 3 Input B E C F D G Out 1 Out 2 Out 3 Result You can also add a clock register time group. TIMEGRP BEF = FFS(Out*); TIMEGRP DATA_GROUP OFFSET = IN 10 BEFORE CLK BEF; This restricts the constraint to registers B, E, and F. Timing & Constraints, 7/22/98 Slide 22

OFFSET Examples (1) 14 ns D Determined by tools Q D Q 40 ns Determined by tools D Q 25 ns D Q CLOCK Upstream Device XILINX DEVICE w The following two UCF files are equivalent: NET CLOCK PERIOD=40; ##External (shown in diagram) NET ADD 0_IN OFFSET = IN 14 AFTER CLOCK; NET ADD 0_OUT OFFSET = OUT 25 BEFORE CLOCK; NET CLOCK PERIOD=40; ##Internal (not shown in diagram): NET ADD 0_IN OFFSET = IN 26 BEFORE CLOCK; NET ADD 0_OUT OFFSET = OUT 15 AFTER CLOCK; Timing & Constraints, 7/22/98 Slide 23 Downstream Device

OFFSET Examples (2) w Wildcard Grouping Specification (UCF only) — — NET ADDR_<*> OFFSET = IN 15 AFTER clk 50; NET ADDR_<*> OFFSET = OUT 35 BEFORE clk 50; w Global Control (PCF only) — — OFFSET = IN 35 ns BEFORE COMP “clk 50” ; OFFSET = OUT 30 ns AFTER COMP “clk 50” ; Timing & Constraints, 7/22/98 Slide 24

Synopsys Support for PERIOD and OFFSET • Synopsys supports this type of system level timing analysis in the. dc scripting file. . dc file . ncf file 1) create_clock -period 125 -waveform {0 62. 5} find(port, "CLK") 2) set_input_delay 125 -clock "CLK" find(port, "NOTRST") 3) set_output_delay 125 -clock "CLK" find(port, "GAG<0>") 1) TIMESPEC TS_CLK = PERIOD : "CLK": 125 : HIGH : 62. 5; 2) NET "CLK" TNM = "CLK"; 3) NET "NOTRST" OFFSET = IN : 125 : AFTER : "CLK"; 4) NET "GAG<0>" OFFSET = OUT : 125 : BEFORE : "CLK"; Timing & Constraints, 7/22/98 Slide 25

Timing Constraints (II) Using FROM: TO and other constraints HDL and M 1. 5, 7/10/98 Slide 26

Timing Path Keywords w Timing constraints are applied to logic paths w Logic paths typically start and stop at pads, registers, latches, and RAM w The tool recognizes the following keywords to define endpoints or time groups: PADS FFS LATCHES RAMS All I/O pads All flip-flops All latches All RAM elements w Keywords can be used globally, and to create design sub-groups Timing & Constraints, 7/22/98 Slide 27

Basic Global Timing Constraints ( using the FROM-TO Syntax) UCF TIMESPEC command using default keywords: TIMESPEC TS_C 2 S=FROM: FFS: TO: FFS: 30; TIMESPEC TS_P 2 S=FROM: PADS: TO: FFS: 25; TIMESPEC TS_P 2 P=FROM: PADS: TO: PADS: 26; TIMESPEC TS_C 2 P=FROM: FFS: TO: PADS: 9; TS_P 2 S TS_C 2 P D Q OUT 1 CLK OUT 2 TS_P 2 P Timing & Constraints, 7/22/98 Slide 28

Basic Global Timing Constraints ( using the FROM-TO Syntax) TIMESPEC TS_F 2 F=FROM: FFS: TO: FFS: 30; w The word TIMESPEC defines the type of specification w The Spec’s name must start with “TS” any alphanumeric after TS is fine. Recommendation: Make the name something you will remember later. w FROM: designates the origin of the path w TO: designates the destination of the path w 30; in ns by default, is the specification. You can use MHz, or even another time spec like TS_C 2 S/2 or TS_C 2 S*2 Timing & Constraints, 7/22/98 Slide 29

Using TNM to create Groups NET clock TNM=clk_group; w Any Keyword element can be made into a ‘group’ for timing purposes w In this example the net ‘clock’ is traced forward to the two flip-flop (FFS). w These flip-flops are ‘timing-named’ (TNM) with the name ‘clk_group’. w They can now be referenced by this TNM in D Q TIMESPECs OUT 1 CLOCK OUT 2 Timing & Constraints, 7/22/98 Slide 30

Using TNM to create Groups. NET clock TNM=clk_group; w These timing groups can overlap, meaning a FFS, LATCHES, RAMS, or PADS can belong to multiple groups if necessary to describe your design’s timing w Time constraints are case sensitive (TNM=abc TNM=ABC) w Groups are ideal for identifying groups of logic that work at different speeds……. (multi-cycle paths and other slow exceptions). Timing & Constraints, 7/22/98 Slide 31

Using TNM_NET to create Groups NET clock TNM_NET=clk_group; w TNM_NET is equivalent to TNM on a net except for pad nets. w When placing a TNM on a pad net the TNM would locate itself on the pad and not trace forward through the buffer to the next synchronous element. TNM_NET was created for this purpose. If you place a TNM_NET on a pad net, it will trace through the buffer to the next synchronous element. w TNM_NET is extremely useful for synthesis designs. The only meaningful net names are the ones directly connected to pads. w TNM_NET can be used in UCF or NCF only. Timing & Constraints, 7/22/98 Slide 32

Multi-Cycle Delays Grouping by net name w Using pattern matching on register’s output net names to create groups. Good for schematics. TIMESPEC TS_MYBUS = FROM: FFS(DATA 0<*>): TO: FFS(MY_REG*): TS_CLK*2; D TS_MYBUS Q MY_REG_0 reg 0 MY_REG_1 D Q reg 1 DATA 0 D CNT 16 Q reg 2 D Q reg 3 Timing & Constraints, 7/22/98 Slide 33 MY_REG_2 MY_REG_3

Multi-Cycle Delays Grouping by instance name w Using INST to create groups. INST pattern matches on the symbol name. Good for Synthesis. INST CNT 16/* TNM=CNT 25; INST reg* TNM=MYREG; TIMESPEC TS_MYBUS= FROM: CNT 25: TO: MYREG: TS_CLK*2; D TS_MYBUS Q MY_REG_0 reg 0 MY_REG_1 D Q reg 1 DATA 0 CNT 16 D Q reg 2 D Q reg 3 Timing & Constraints, 7/22/98 Slide 34 MY_REG_2 MY_REG_3

Slow Exceptions w Slow Exceptions are FROM: TOs that define a different delay for portion of the design. The majority of the design has PERIOD. w Preferred methodology; PAR and TRCE will execute Example 1: Using FROM: TO’s only -- OK, but not best method faster. 60 ns 30 ns IN D Q FROM: flop 1: TO: flop 2: 30 D Q FROM: flop 2: TO: flop 3: 60 D OUT Q CLK Example 2: Using PERIOD with a FROM: TO Slow Exception -- BEST 60 ns 30 ns IN D Q D NET CLK PERIOD=30 CLK Timing & Constraints, 7/22/98 Slide 35 Q FROM: flop 2: TO: flop 3: 60 D Q OUT

Slow Exceptions: Multi-Cycle Delays with Clock Enables w Forward trace on the clock enable to create a slow exception NET “CLK_EN” TNM=SLOW; NET “CLK” TNM = FAST; TIMESPEC TS 01=PERIOD FAST 30; TIMESPEC TS 02=FROM: SLOW: TO: SLOW: TS 01*2; 60 ns 30 ns IN D CLK Q D TNM=FAST CE D Q TNM=FAST TNM=SLOW CE Q OUT TNM=FAST TNM=SLOW CLK_EN Timespecs applying to elements with more than one TNM wi with a priority system……. discussed later. Timing & Constraints, 7/22/98 Slide 36

Specific Delays from one group to another w Qualifying predefined groups to create path-specific constraints: TIMESPEC TS_FIFOS = FROM: RAMS(FIFORAM<*>): TO: FFS(MY_REG*): 25; Note: The pattern matching is on the output signal of the FFS/RAMS, not the symbol name. Use INST to pattern match on the symbol name. D Q MY_REG_0 reg 0 MY_REG_1 D Q reg 1 MYFIFORAM D Q MY_REG_2 reg 2 D Q reg 3 Timing & Constraints, 7/22/98 Slide 37 MY_REG_3

Specific Delays going through specific logic (TPTHRU) w Forces the path through specific logic. w The TPTHRU attribute is attached to net / instance / macro in top blob. NET $3 M 17/ON_THE_WAY TPTHRU = ABC; TIMESPEC TS_FIFOS=FROM: RAMS(FIFORAM<*>): THRU: ABC TO: FFS(MY_REG*): 25; FIFORAM MYFIFO TPTHRU=abc D Q MY_REG_0 reg 0 MY_REG_1 D Q reg 2 Timing & Constraints, 7/22/98 Slide 38 MY_REG_2

Specific Delays Excluding Logic w You can create subgroups based on names with “EXCEPT” w Example: Assume this design has several data busses that all start with “DATA”. Use the EXCEPT command to create a group with all the pads except the data pads. — — — TIMEGROUP CTRL_PADS = PADS: EXCEPT (DATA*); TIMEGROUP DATAPINS = PADS(DATA*); TIMESPEC TS_IO 1=FROM: CTRL_PADS: TO: FFS: 20; TIMESPEC TS_IO 2=FROM: FFS: TO: CTRL_PADS: 20; TIMESPEC TS_IO 3=FROM: CTRL_PADS: TO: CTRL_PADS: 30; TIMESPEC TS_IODATA=FROM: DATAPINS: TO: FFS: 15; Timing & Constraints, 7/22/98 Slide 39

Constraining Between Rising & Falling Clock Edges w Define clock groups, the (“*”) covers all FFS in your design — — TIMEGRP RFFS = RISING FFS (“*”); TIMEGRP FFFS = FALLING FFS (“*”); w Define timing constraints — — TIMESPEC TS_R 2 F=FROM: RFFS: TO: FFFS: 30; TIMESPEC TS_F 2 R=FROM: FFFS: TO: RFFS: 30; D Q OUT 1 w Remember, the PERIOD constraint will automatically account for two-phase clocks. Timing & Constraints, 7/22/98 Slide 40

Constraining Between Multiple Clock Domains w Define clock groups — — NET CLK_A TNM=A_GRP; NET CLK_B TNM=B_GRP; w Define timing constraints — — — TIMESPEC TS_CLKA=PERIOD A_GRP 20; TIMESPEC TS_CLKB=PERIOD B_GRP TS_CLKA*2; TIMESPEC TS_CLKA 2 B=FROM: A_GRP: TO: B_GRP: 20; D CLK_A CLK_B Timing & Constraints, 7/22/98 Slide 41 Q D Q D Q OUT 1

Creating new synchronous points (TPSYNC) Allows definition of synchronous points that are not FFS, RAMS, PADS or LATCHES. —Commonly used with three-state buffers. —Example: NET $3 M 17/BLUE TPSYNC = BLUE_S; TIMESPEC TS_1 A=FROM: FFS: TO: BLUE_S : 15 ; $3 M 17/BLUE D Q comb_b TS_1 A Timing & Constraints, 7/22/98 Slide 42 RAM/ FFS/ PADS/ LATCH

Ignoring Paths (TIG) w Never changing input signal NET CHIP_MODE TIG; w Ignore a signal for a specific timespec NET SLOW_SIG TIG=TS_01; w Ignore false paths between registers TIMESPEC TS_TIG 1=FROM: FFS(REGA*): TO: FFS(REGB*): TIG; Note: May have to use INST to create groups for synthesis designs. Timing & Constraints, 7/22/98 Slide 43

Controlling False Paths (TPTHRU) w Design has bi-directional bus with sets of registers in different blocks. There is a false path from control registers through the TBUF to the status registers. NET DATA_BUS<*> TPTHRU = DATABUS; TIMESPEC TS_TIG=FROM: FFS: THRU: DATABUS: TO: FFS: TIG; Status Registers Control Register Control_Enable DATA_BUS(7: 0) Timing & Constraints, 7/22/98 Slide 44 Status_Enable

Timing Constraint Priority (1) w It is legal to constrain the same paths more than once —Known as a constraint conflict —Multiple sources constraining the same path – UCF and schematic could constrain same path —Multiple constraints on one net within one source w Resolution of conflicting constraints from multiple sources: —Lowest Priority input netlist or. ncf file. ucf file —Highest Priority. pcf file (usually from MAP) Note: this priority only applies to timespecs with identical TSidentfiers (e. g. TS_03 =…) Timing & Constraints, 7/22/98 Slide 45

Timing Constraint Priority (2) w Within a particular source: —Highest Priority by user defined groups Timing ignores (TIG) FROM: THRU: TO specs Source and destination defined Source or destination defined Source and destination are pre- FROM: TO specs Source and destination defined Source or destination defined Source and destination are pre. Specific data IOB Time group of data IOBs All data IOBs Timing & Constraints, 7/22/98 Slide 46 PERIOD specs OFFSET specs

Timing Constraint Priority (3) w Same path constrained with different FROM: TO statements — Highest Priority - Source and destination defined by user - Source or destination defined by user — Lowest Priority - Source and destination are predefined groups w You can explicitly assign priorities — Syntax – (SOME_NORMAL_TIMESPEC) : PRIORITY : integer — Low numbers specify high priority (1 thru about 2 million) — To match timespec the priority scheme in XACT 6. 0, use priority set to the time allowed in the timespec. – If the time constraint is 10, set the priority to 10 Timing & Constraints, 7/22/98 Slide 47

SKEW w SKEW is the difference in the arrival time of the clock pulse between a source and destination If the clock pulse arrives at the source reg first register (or element) D Qother synchronous D Q followed by the dest reg, then it is “positive skew”; if it arrives at the dest followed by the source, then it is “negative skew”. w Some Positive skew can be beneficial; it will decrease the. Clock required setup time: @ Source Register Clock @ Destination Register Clock skew w Too much Positive skew can create a race Clock @ Source Register condition, hold-time violation: B Clock @ Destination Register A Clock skew Data “A” arrives at the destination, but it could be overridden by Data “B”, which is meant for the next pulse at the destination reg. Timing & Constraints, 7/22/98 Slide 48

SKEW (II) w Negative skew is usually undesirable; it will increase the required setup time: Clock @ Source Register Clock @ Destination Register Clock skew w If you use the global clock resources, then there should be no danger of hold-time violations for internal paths w TRACE can check for race conditions; set env. variable XILINX_DORACECHECK to activate this (same environment variable will activate skewchecking). Timing & Constraints, 7/22/98 Slide 49

MAXSKEW: Limiting SKEW w Signal SKEW may also be constrained using the MAXSKEW constraint — NET $1 I 3245/$SIG_6 MAXSKEW=3; — I. e. specifies a maximum of 3 ns difference between the source of net $1 I 3245/$SIG_6 and all its destinations is permissible w May use to control skew of logic driven clocks (or any clock using non-global resources) w Cannot constrain skew of global nets (Makes no sense as skew is fixed) Timing & Constraints, 7/22/98 Slide 50

Reporting SKEW in TRACE w 2. 1 i TRACE will automatically account for clock skew on PERIOD constraints. Use the -skew switch or environment variable. XILINX_DOSKEWCHECK=1 (or XILINX_DORACECHECK). w Avoid using environment variable with PAR if there are IBUF clocks. PAR’s timing score may oscillate. w If you use the -skew switch with TRACE, remember that the timing score may be different than the score given by PAR (it could be better or worse). Timing & Constraints, 7/22/98 Slide 51

Prorating Constraints w The tools will allow the user to prorate timing delay characteristics based on known environmental parameters. This is available only in the XC 4000 XL family. w Voltage: Allows the user to specify the operating voltage. UCF syntax: VOLTAGE = value [units] w Temperature: Allows the user to specify the operating temperature. UCF syntax: TEMPERATURE = value [C|F|K] Celsius is the default. Timing & Constraints, 7/22/98 Slide 52

Placement & Other Constraints Using LOC, BLKNM, and other physical constraints HDL and M 1. 5, 7/10/98 Slide 53

Pin Location Constraints w “LOC” constraint used to locate pins: —From a Schematic attach the attribute “LOC=P 12” to the pins you wish to lock down —I/O constraint based on net name in the. UCF file NET IOBLOCK/DATA 0_IN LOC=P 12; —I/O constraint based on the instance name in the. UCF file INST IOBLOCK/DATA_IN_PAD LOC=P 12; w 2. 1 i produces a. PAD file. Design Manager provides a utility to translate the. PAD file to a. UCF file that contains the pin assignments. In the Design Manager, select the ‘Design’ menu, click on ‘Lock Pins’. This will generate the ucf file. However, the utility will always assume the I/O net Timing & Constraints, 7/22/98 Slide 54

Other Location Constraints w “LOC” constraint used to locate: —BUFTs, FFs, MAPs, CLBs, PADs, WANDs, decoders, global buffer —single components (e. g. CLBs) INST U 45 LOC=CLB_R 1 C 5; —ranges of components (but not IOs) INST U 46 LOC=CLB_R 2 C 2: CLB_R 4 C 6; —multiple sites for single component INST U 50 LOC=CLB_R 1 C 1; CLB_R 2 C 1; —I/O constraint based on net name NET IOBLOCK/DATA 0_IN LOC=P 12; Timing & Constraints, 7/22/98 Slide 55

Prohibit Location Constraints w “PROHIBIT” Disallows the use of these sites within PAR: —CLBs, PADs, BUFTs, decoders, global buffer, function blocks/macrocells —single components (e. g. CLBs) CONFIG PROHIBIT=CLB_R 1 C 5; —ranges of components (but not IOs) CONFIG PROHIBIT=CLB_R 2 C 2: CLB_R 4 C 6; —I/O constraint based on net name CONFIG PROHIBIT=P 12; Note: CONFIG PROHIBIT has specific limits depending upon the device. Please reference the “Libraries Guide” for these limits. Timing & Constraints, 7/22/98 Slide 56

Mapping Constraints w Force logic into the same CLB. — Sometimes MAP doesn’t make the best decisions. This allows the user to map logic together. w Syntax INST state_reg_1 BLKNM=STATE 1; INST state_reg_2 BLKNM=STATE 1; INST my_FMAP_logic BLKNM=STATE 1; #Can constrain FMAPs but not gates w This will force my_FMAP, state_reg_1, state_reg_2, and into the same CLB (“STATE 1”). Note: The remaining resources are still up for grabs by MAP (in this case, one of the FG’s is still available). Timing & Constraints, 7/22/98 Slide 57

Implementation Constraints w Physical implementation may be controlled in the UCF file, such as: — FAST : Set Faster IO Slew rate — PART : Define Part-type to be used – e. g. INST $1 I 87/OBUF FAST – e. g. CONFIG PART=4005 E-PQ 160 C-5; — BUFG : Force signal to onto global net (CPLD only) – e. g. INST clkgen/fastclk BUFG; — INIT only) : Define initial RAM/ROM Contents (primitives – e. g. INST $1 I 3245/ROM 2 INIT = 5555; w Such Physical constraints may be Architecture dependent Timing & Constraints, 7/22/98 Slide 58

Conclusion Overview of Constraints HDL and M 1. 5, 7/10/98 Slide 59

Basic constraints file w Most generic timing constraints for fastest PAR runtime NET CLK 1 PERIOD = 40; NET OUT* OFFSET = OUT 13 AFTER CLK 1; TIMESPEC TS 01 = FROM PADS TO PADS 40; Timing & Constraints, 7/22/98 Slide 60

More specific constraints file w Clocks NET CLK TNM=CLK; NET CLK 2 TNM=CLK 2; TIMESPEC TS_CLK 01=PERIOD CLK 40; TIMESPEC TS_CLK 02=PERIOD CLK 2 50; w Ignore paths between 2 async clocks TIMESPEC TS_TIG 1=FROM: CLK: TO: CLK 2: TIG; TIMESPEC TS_TIG 2=FROM: CLK 2: TO: CLK: TIG; w Generic path to outputs TIMESPEC TS_IO 1=FROM: FFS: TO: PADS: 20; w Two cycle path to slow outputs TIMESPEC TS_IO 2=FROM: FFS: TO: PADS(SLOW*): TS_IO 1*2; Timing & Constraints, 7/22/98 Slide 61

More specific constraints file (cont. ) w Offset for late input signal NET LATE_INPUT OFFSET=IN: 30: AFTER: CLK; w Ignore static input signal NET CHIP_MODE TIG; w Static control registers INST CONTROL_BLOCK/CTRL_REG* TNM=CTRL_REG; TIMESPEC TS_CLK 03 = FROM: CTRL_REG: TO: FFS=TS_CLK 01*2; w Fast OBUF attached to component INST RAM_CS FAST; w Prohibit Pins CONFIG PROHIBIT = P 6; Timing & Constraints, 7/22/98 Slide 62

ISSUES to be aware of w The. ucf file will be copied into the new revision directory as <design_name>. ucf, where the <design_name> is the name of the input netlist. w The design Manager can only use <design_name>. ucf for implementation in the Revision. w If the ucf file has errors, the ucf in the Revision directory needs to be modified, and NOT the original. Timing & Constraints, 7/22/98 Slide 63

ISSUES to be aware of (II) w TNM and PERIOD constraint cannot forward-trace through IBUF. TNM cannot forward-trace through BUFG either. IBUF TNM=; PERIOD Must apply to output net (of IBUF/BUFG) or use TNM_NET. BUFG TNM=xxx w Use the “-u” switch with TRCE to report unconstrained paths (or Report Paths Not Covered In Timing Constraints for TA) w The -u will not necessarily contain every unconstrained path ( the static carry logic path in earlier schematic; STARTUP path). It essentially shows all “constrainable” unconstrained paths, such as paths that could have been reported with Timing & Constraints, 7/22/98 Slide 64

ISSUES to be aware of (III) w Timing report often does not show 100% coverage of. Definition: connections A “connection” is a source/driver pairing. The following has 13 CLOCK connections (paths internal to IOB/CLB are not connections): 4 D Q 5 D Q 6 Function 7 Generator 3 2 8 1 9 TIG 10 12 Function Generator OUT 1 11 OUT 2 13 OUT 2 STARTUP CY 4 Function Generator Examine-CI Not covered by usual set of CY 4 timespecs (can use MAXDELAY Force-1 on net to constrain) Removed from analysis Timing & Constraints, 7/22/98 Slide 65 Static signal driving LUT; not covered by usual set of timespecs (exotic case)

Summary w All Constraints accessible from single constraints file w All Xilinx features may be constrained from constraints file w Full Time. Spec support provided from Constraints file w Improved Time. Spec capability provided w Refer to Chapter 12 (Attributes, Constraints and Carry Logic) of the Xilinx Libraries Guide for a full list of all supported constraints and examples of syntax Timing & Constraints, 7/22/98 Slide 66

Timing & Constraints, 7/22/98 Slide 67

Timing & Constraints, 7/22/98 Slide 68

Documentation w Constraints Guide: Quick Start Guide appendix H. w Using Timing Constraints: Developmental System Reference Guide chapter 6. w Timing Analyzer: Timing Analyzer Reference/User Guide. w TRCE: Developmental System Reference Guide chapter 11. w Refer to Chapter 12 (Attributes, Constraints and Carry Logic) of the Xilinx Libraries Guide for a full list of all supported constraints and examples of syntax Timing & Constraints, 7/22/98 Slide 69