1FileProjectName 2VHDLAHDLVerlog Maxplusgraphic Editor MaxplusText Editor MaxplusWaveform Editor

设计过程 1、输入项目文件名(File/Project/Name) 2、输入源文件(图形、VHDL、AHDL、Verlog和波形输入方式 ) (Max+plusⅡ/graphic Editor, Max+plusⅡ/Text Editor, Max+plusⅡ/Waveform Editor) 3、指定器件型号(Assign/Device) 4、保存并检查源文件(File/project/Save & Check)

6、指定管脚(Max+plusⅡ/Floorplan Editor) 7、保存和编译源文件(File/project/Save & Compile) 8、生成波形文件(Max+plusⅡ/Waveform Editor) 9、仿真(Max+plusⅡ/Simulator) 10、下载配置(Max+plusⅡ/Programmer)

用与门、或门和非门构成异或门 ARCHITECTURE structure OF xor_gate IS COMPONENT not_gate PORT(a: IN BIT; b: OUT BIT); END COMPONENT; COMPONENT and_gate PORT(a, b: IN BIT; c: OUT BIT); END COMPONENT;

COMPONENT or_gate PORT(a, b: IN BIT; c: OUT BIT); END COMPONENT; SIGNAL na, nb: BIT; SIGNAL 1 c 1, c 2: BIT; BEGIN u 1: not_gate PORT MAP(a, na); u 2: not_gate PORT MAP(a, nb); u 3: and_gate PORT MAP(a, nb, c 1); u 4: and_gate PORT MAP(b, na, c 2); u 1: or_gate PORT MAP(c 1, c 2, c); END structure