15 213 The course that gives CMU its

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15 -213 “The course that gives CMU its Zip!” Machine-Level Programming I: Introduction Sept.

15 -213 “The course that gives CMU its Zip!” Machine-Level Programming I: Introduction Sept. 10, 2002 Topics n n Assembly Programmer’s Execution Model Accessing Information l Registers l Memory n class 05. ppt Arithmetic operations

IA 32 Processors Totally Dominate Computer Market Evolutionary Design n Starting in 1978 with

IA 32 Processors Totally Dominate Computer Market Evolutionary Design n Starting in 1978 with 8086 Added more features as time goes on Still support old features, although obsolete Complex Instruction Set Computer (CISC) n Many different instructions with many different formats l But, only small subset encountered with Linux programs n n – 2– Hard to match performance of Reduced Instruction Set Computers (RISC) But, Intel has done just that! 15 -213, F’ 02

X 86 Evolution: Programmer’s View Name Date Transistors 8086 1978 29 K 16 -bit

X 86 Evolution: Programmer’s View Name Date Transistors 8086 1978 29 K 16 -bit processor. Basis for IBM PC & DOS n Limited to 1 MB address space. DOS only gives you 640 K n 80286 1982 134 K Added elaborate, but not very useful, addressing scheme n Basis for IBM PC-AT and Windows n 386 1985 275 K Extended to 32 bits. Added “flat addressing” n Capable of running Unix n Linux/gcc uses no instructions introduced in later models n – 3– 15 -213, F’ 02

X 86 Evolution: Programmer’s View Name 486 Date Transistors 1989 1. 9 M Pentium

X 86 Evolution: Programmer’s View Name 486 Date Transistors 1989 1. 9 M Pentium 1993 3. 1 M Pentium/MMX n 1997 4. 5 M Added special collection of instructions for operating on 64 -bit vectors of 1, 2, or 4 byte integer data Pentium. Pro 1995 6. 5 M Added conditional move instructions n Big change in underlying microarchitecture n – 4– 15 -213, F’ 02

X 86 Evolution: Programmer’s View Name Date Transistors Pentium III 1999 8. 2 M

X 86 Evolution: Programmer’s View Name Date Transistors Pentium III 1999 8. 2 M Added “streaming SIMD” instructions for operating on 128 -bit vectors of 1, 2, or 4 byte integer or floating point data n Our fish machines n Pentium 4 n – 5– 2001 42 M Added 8 -byte formats and 144 new instructions for streaming SIMD mode 15 -213, F’ 02

X 86 Evolution: Clones Advanced Micro Devices (AMD) n Historically l AMD has followed

X 86 Evolution: Clones Advanced Micro Devices (AMD) n Historically l AMD has followed just behind Intel l A little bit slower, a lot cheaper n Recently l Recruited top circuit designers from Digital Equipment Corp. l Exploited fact that Intel distracted by IA 64 l Now are close competitors to Intel n – 6– Developing own extension to 64 bits 15 -213, F’ 02

X 86 Evolution: Clones Transmeta n Recent start-up l Employer of Linus Torvalds n

X 86 Evolution: Clones Transmeta n Recent start-up l Employer of Linus Torvalds n Radically different approach to implementation l Translates x 86 code into “Very Long Instruction Word” (VLIW) code l High degree of parallelism n – 7– Shooting for low-power market 15 -213, F’ 02

New Species: IA 64 Name Itanium Date Transistors 2001 10 M Extends to IA

New Species: IA 64 Name Itanium Date Transistors 2001 10 M Extends to IA 64, a 64 -bit architecture n Radically new instruction set designed for high performance n Will be able to run existing IA 32 programs n l On-board “x 86 engine” n Joint project with Hewlett-Packard Itanium 2 n – 8– 2002 221 M Big performance boost 15 -213, F’ 02

Assembly Programmer’s View CPU Memory Addresses Registers E I P Data Condition Codes Instructions

Assembly Programmer’s View CPU Memory Addresses Registers E I P Data Condition Codes Instructions Object Code Program Data OS Data Stack Programmer-Visible State n EIP Program Counter l Address of next instruction n Register File l Heavily used program data n Condition Codes l Store status information about – 9– most recent arithmetic operation l Used for conditional branching n Memory l Byte addressable array l Code, user data, (some) OS data l Includes stack used to support procedures 15 -213, F’ 02

Turning C into Object Code in files p 1. c p 2. c n

Turning C into Object Code in files p 1. c p 2. c n Compile with command: gcc -O p 1. c p 2. c -o p n l Use optimizations (-O) l Put resulting binary in file p text C program (p 1. c p 2. c) Compiler (gcc -S) text Asm program (p 1. s p 2. s) Assembler (gcc or as) binary Object program (p 1. o p 2. o) Static libraries (. a) Linker (gcc or ld) binary – 10 – Executable program (p) 15 -213, F’ 02

Compiling Into Assembly C Code int sum(int x, int y) { int t =

Compiling Into Assembly C Code int sum(int x, int y) { int t = x+y; return t; } Generated Assembly _sum: pushl %ebp movl %esp, %ebp movl 12(%ebp), %eax addl 8(%ebp), %eax movl %ebp, %esp popl %ebp ret Obtain with command gcc -O -S code. c Produces file code. s – 11 – 15 -213, F’ 02

Assembly Characteristics Minimal Data Types n “Integer” data of 1, 2, or 4 bytes

Assembly Characteristics Minimal Data Types n “Integer” data of 1, 2, or 4 bytes l Data values l Addresses (untyped pointers) n n Floating point data of 4, 8, or 10 bytes No aggregate types such as arrays or structures l Just contiguously allocated bytes in memory Primitive Operations n n Perform arithmetic function on register or memory data Transfer data between memory and register l Load data from memory into register l Store register data into memory n Transfer control l Unconditional jumps to/from procedures l Conditional branches – 12 – 15 -213, F’ 02

Object Code for sum Assembler n Translates. s into. o n Some libraries are

Object Code for sum Assembler n Translates. s into. o n Some libraries are dynamically linked 0 x 401040 <sum>: n Binary encoding of each instruction 0 x 55 • Total of 13 0 x 89 n Nearly-complete image of executable bytes 0 xe 5 code • Each 0 x 8 b instruction 1, n Missing linkages between code in 0 x 45 2, or 3 bytes different files 0 x 0 c • Starts at 0 x 03 address Linker 0 x 45 0 x 401040 0 x 08 n Resolves references between files 0 x 89 n Combines with static run-time 0 xec libraries 0 x 5 d l E. g. , code for malloc, printf 0 xc 3 l Linking occurs when program begins execution – 13 – 15 -213, F’ 02

Machine Instruction Example C Code int t = x+y; n Add two signed integers

Machine Instruction Example C Code int t = x+y; n Add two signed integers Assembly addl 8(%ebp), %eax Similar to expression x += y n Add 2 4 -byte integers l “Long” words in GCC parlance l Same instruction whether signed or unsigned n Operands: x: Register %eax y: Memory M[%ebp+8] t: Register %eax » Return function value in %eax 0 x 401046: 03 45 08 Object Code 3 -byte instruction n Stored at address 0 x 401046 n – 14 – 15 -213, F’ 02

Disassembling Object Code Disassembled 00401040 <_sum>: 0: 55 1: 89 e 5 3: 8

Disassembling Object Code Disassembled 00401040 <_sum>: 0: 55 1: 89 e 5 3: 8 b 45 0 c 6: 03 45 08 9: 89 ec b: 5 d c: c 3 d: 8 d 76 00 push mov add mov pop ret lea %ebp %esp, %ebp 0 xc(%ebp), %eax 0 x 8(%ebp), %eax %ebp, %esp %ebp 0 x 0(%esi), %esi Disassembler objdump -d p n n – 15 – Useful tool for examining object code Analyzes bit pattern of series of instructions Produces approximate rendition of assembly code Can be run on either a. out (complete executable) or. o file 15 -213, F’ 02

Alternate Disassembly Disassembled Object 0 x 401040: 0 x 55 0 x 89 0

Alternate Disassembly Disassembled Object 0 x 401040: 0 x 55 0 x 89 0 xe 5 0 x 8 b 0 x 45 0 x 0 c 0 x 03 0 x 45 0 x 08 0 x 89 0 xec 0 x 5 d 0 xc 3 0 x 401040 0 x 401041 0 x 401043 0 x 401046 0 x 401049 0 x 40104 b 0 x 40104 c 0 x 40104 d <sum>: <sum+1>: <sum+3>: <sum+6>: <sum+9>: <sum+11>: <sum+12>: <sum+13>: push mov add mov pop ret lea %ebp %esp, %ebp 0 xc(%ebp), %eax 0 x 8(%ebp), %eax %ebp, %esp %ebp 0 x 0(%esi), %esi Within gdb Debugger gdb p disassemble sum Disassemble procedure x/13 b sum n Examine the 13 bytes starting at sum n – 16 – 15 -213, F’ 02

What Can be Disassembled? % objdump -d WINWORD. EXE: file format pei-i 386 No

What Can be Disassembled? % objdump -d WINWORD. EXE: file format pei-i 386 No symbols in "WINWORD. EXE". Disassembly of section. text: 30001000 <. text>: 30001000: 55 30001001: 8 b ec 30001003: 6 a ff 30001005: 68 90 10 00 30 3000100 a: 68 91 dc 4 c 30 n n – 17 – push mov push %ebp %esp, %ebp $0 xffff $0 x 30001090 $0 x 304 cdc 91 Anything that can be interpreted as executable code Disassembler examines bytes and reconstructs assembly source 15 -213, F’ 02

Moving Data %eax %edx Moving Data movl Source, Dest: n n Move 4 -byte

Moving Data %eax %edx Moving Data movl Source, Dest: n n Move 4 -byte (“long”) word Lots of these in typical code Operand Types n Immediate: Constant integer data l Like C constant, but prefixed with ‘$’ %ecx %ebx %esi %edi %esp %ebp l E. g. , $0 x 400, $-533 l Encoded with 1, 2, or 4 bytes n Register: One of 8 integer registers l But %esp and %ebp reserved for special use l Others have special uses for particular instructions n Memory: 4 consecutive bytes of memory l Various “address modes” – 18 – 15 -213, F’ 02

movl Operand Combinations Source movl C Analog movl $0 x 4, %eax temp =

movl Operand Combinations Source movl C Analog movl $0 x 4, %eax temp = 0 x 4; movl $-147, (%eax) *p = -147; Imm Reg Mem movl %eax, %edx temp 2 = temp 1; movl %eax, (%edx) *p = temp; Mem Reg movl (%eax), %edx temp = *p; n – 19 – Destination Cannot do memory-memory transfers with single instruction 15 -213, F’ 02

Simple Addressing Modes Normal (R) Mem[Reg[R]] Register R specifies memory address movl (%ecx), %eax

Simple Addressing Modes Normal (R) Mem[Reg[R]] Register R specifies memory address movl (%ecx), %eax n Displacement D(R) Mem[Reg[R]+D] Register R specifies start of memory region n Constant displacement D specifies offset movl 8(%ebp), %edx n – 20 – 15 -213, F’ 02

Using Simple Addressing Modes void swap(int *xp, int *yp) { int t 0 =

Using Simple Addressing Modes void swap(int *xp, int *yp) { int t 0 = *xp; int t 1 = *yp; *xp = t 1; *yp = t 0; } swap: pushl %ebp movl %esp, %ebp pushl %ebx movl movl Set Up 12(%ebp), %ecx 8(%ebp), %edx (%ecx), %eax (%edx), %ebx %eax, (%edx) %ebx, (%ecx) movl -4(%ebp), %ebx movl %ebp, %esp popl %ebp ret – 21 – Body Finish 15 -213, F’ 02

Understanding Swap void swap(int *xp, int *yp) { int t 0 = *xp; int

Understanding Swap void swap(int *xp, int *yp) { int t 0 = *xp; int t 1 = *yp; *xp = t 1; *yp = t 0; } • • • Offset Stack 12 yp 8 xp 4 Rtn adr 0 Old %ebp Register %ecx %edx %eax %ebx – 22 – Variable yp xp t 1 t 0 %ebp -4 Old %ebx movl movl 12(%ebp), %ecx 8(%ebp), %edx (%ecx), %eax (%edx), %ebx %eax, (%edx) %ebx, (%ecx) # # # ecx edx eax ebx *xp *yp = = = yp xp *yp (t 1) *xp (t 0) eax ebx 15 -213, F’ 02

Address Understanding Swap 123 0 x 124 456 0 x 120 0 x 11

Address Understanding Swap 123 0 x 124 456 0 x 120 0 x 11 c %eax 0 x 118 Offset %edx %ecx %ebx %esi – 23 – 12 0 x 120 0 x 110 xp 8 0 x 124 0 x 10 c 4 Rtn adr 0 x 108 0 0 x 104 -4 %esp %ebp yp %ebp %edi 0 x 114 0 x 104 movl movl 12(%ebp), %ecx 8(%ebp), %edx (%ecx), %eax (%edx), %ebx %eax, (%edx) %ebx, (%ecx) # # # ecx edx eax ebx *xp *yp 0 x 100 = = = yp xp *yp (t 1) *xp (t 0) eax ebx 15 -213, F’ 02

Address Understanding Swap 123 0 x 124 456 0 x 120 0 x 11

Address Understanding Swap 123 0 x 124 456 0 x 120 0 x 11 c %eax 0 x 118 Offset %edx %ecx 0 x 120 %ebx %esi – 24 – 12 0 x 120 0 x 110 xp 8 0 x 124 0 x 10 c 4 Rtn adr 0 x 108 0 0 x 104 -4 %esp %ebp yp %ebp %edi 0 x 114 0 x 104 movl movl 12(%ebp), %ecx 8(%ebp), %edx (%ecx), %eax (%edx), %ebx %eax, (%edx) %ebx, (%ecx) # # # ecx edx eax ebx *xp *yp 0 x 100 = = = yp xp *yp (t 1) *xp (t 0) eax ebx 15 -213, F’ 02

Address Understanding Swap 123 0 x 124 456 0 x 120 0 x 11

Address Understanding Swap 123 0 x 124 456 0 x 120 0 x 11 c %eax 0 x 118 %edx 0 x 124 %ecx 0 x 120 Offset %ebx %esi – 25 – 12 0 x 120 0 x 110 xp 8 0 x 124 0 x 10 c 4 Rtn adr 0 x 108 0 0 x 104 -4 %esp %ebp yp %ebp %edi 0 x 114 0 x 104 movl movl 12(%ebp), %ecx 8(%ebp), %edx (%ecx), %eax (%edx), %ebx %eax, (%edx) %ebx, (%ecx) # # # ecx edx eax ebx *xp *yp 0 x 100 = = = yp xp *yp (t 1) *xp (t 0) eax ebx 15 -213, F’ 02

Address Understanding Swap 123 0 x 124 456 0 x 120 0 x 11

Address Understanding Swap 123 0 x 124 456 0 x 120 0 x 11 c %eax 456 %edx 0 x 124 %ecx 0 x 120 0 x 118 Offset %ebx %esi – 26 – 12 0 x 120 0 x 110 xp 8 0 x 124 0 x 10 c 4 Rtn adr 0 x 108 0 0 x 104 -4 %esp %ebp yp %ebp %edi 0 x 114 0 x 104 movl movl 12(%ebp), %ecx 8(%ebp), %edx (%ecx), %eax (%edx), %ebx %eax, (%edx) %ebx, (%ecx) # # # ecx edx eax ebx *xp *yp 0 x 100 = = = yp xp *yp (t 1) *xp (t 0) eax ebx 15 -213, F’ 02

Address Understanding Swap 123 0 x 124 456 0 x 120 0 x 11

Address Understanding Swap 123 0 x 124 456 0 x 120 0 x 11 c %eax 456 %edx 0 x 124 %ecx 0 x 120 %ebx 0 x 118 Offset 123 %esi – 27 – 12 0 x 120 0 x 110 xp 8 0 x 124 0 x 10 c 4 Rtn adr 0 x 108 0 0 x 104 -4 %esp %ebp yp %ebp %edi 0 x 114 0 x 104 movl movl 12(%ebp), %ecx 8(%ebp), %edx (%ecx), %eax (%edx), %ebx %eax, (%edx) %ebx, (%ecx) # # # ecx edx eax ebx *xp *yp 0 x 100 = = = yp xp *yp (t 1) *xp (t 0) eax ebx 15 -213, F’ 02

Address Understanding Swap 456 0 x 124 456 0 x 120 0 x 11

Address Understanding Swap 456 0 x 124 456 0 x 120 0 x 11 c %eax 456 %edx 0 x 124 %ecx 0 x 120 %ebx 0 x 118 Offset 123 %esi – 28 – 12 0 x 120 0 x 110 xp 8 0 x 124 0 x 10 c 4 Rtn adr 0 x 108 0 0 x 104 -4 %esp %ebp yp %ebp %edi 0 x 114 0 x 104 movl movl 12(%ebp), %ecx 8(%ebp), %edx (%ecx), %eax (%edx), %ebx %eax, (%edx) %ebx, (%ecx) # # # ecx edx eax ebx *xp *yp 0 x 100 = = = yp xp *yp (t 1) *xp (t 0) eax ebx 15 -213, F’ 02

Address Understanding Swap 456 0 x 124 123 0 x 120 0 x 11

Address Understanding Swap 456 0 x 124 123 0 x 120 0 x 11 c %eax 456 %edx 0 x 124 %ecx 0 x 120 %ebx 0 x 118 Offset 123 %esi – 29 – 12 0 x 120 0 x 110 xp 8 0 x 124 0 x 10 c 4 Rtn adr 0 x 108 0 0 x 104 -4 %esp %ebp yp %ebp %edi 0 x 114 0 x 104 movl movl 12(%ebp), %ecx 8(%ebp), %edx (%ecx), %eax (%edx), %ebx %eax, (%edx) %ebx, (%ecx) # # # ecx edx eax ebx *xp *yp 0 x 100 = = = yp xp *yp (t 1) *xp (t 0) eax ebx 15 -213, F’ 02

Indexed Addressing Modes Most General Form D(Rb, Ri, S) Mem[Reg[Rb]+S*Reg[Ri]+ D] D: Constant “displacement”

Indexed Addressing Modes Most General Form D(Rb, Ri, S) Mem[Reg[Rb]+S*Reg[Ri]+ D] D: Constant “displacement” 1, 2, or 4 bytes n Rb: Base register: Any of 8 integer registers n Ri: Index register: Any, except for %esp n l Unlikely you’d use %ebp, either n S: Scale: 1, 2, 4, or 8 Special Cases – 30 – (Rb, Ri) Mem[Reg[Rb]+Reg[Ri]] D(Rb, Ri) Mem[Reg[Rb]+Reg[Ri]+D] (Rb, Ri, S) Mem[Reg[Rb]+S*Reg[Ri]] 15 -213, F’ 02

Address Computation Examples %edx 0 xf 000 %ecx – 31 – 0 x 100

Address Computation Examples %edx 0 xf 000 %ecx – 31 – 0 x 100 Expression Computation Address 0 x 8(%edx) 0 xf 000 + 0 x 8 0 xf 008 (%edx, %ecx) 0 xf 000 + 0 x 100 0 xf 100 (%edx, %ecx, 4) 0 xf 000 + 4*0 x 100 0 xf 400 0 x 80(, %edx, 2) 2*0 xf 000 + 0 x 80 0 x 1 e 080 15 -213, F’ 02

Address Computation Instruction leal Src, Dest n n Src is address mode expression Set

Address Computation Instruction leal Src, Dest n n Src is address mode expression Set Dest to address denoted by expression Uses n Computing address without doing memory reference l E. g. , translation of p = &x[i]; n Computing arithmetic expressions of the form x + k*y l k = 1, 2, 4, or 8. – 32 – 15 -213, F’ 02

Some Arithmetic Operations Format Computation Two Operand Instructions addl Src, Dest subl Src, Dest

Some Arithmetic Operations Format Computation Two Operand Instructions addl Src, Dest subl Src, Dest imull Src, Dest sarl Src, Dest shrl Src, Dest xorl Src, Dest andl Src, Dest orl Src, Dest – 33 – Dest Dest Dest = = = = = Dest Dest Dest + Src - Src * Src << Src Also called shll >> Src Arithmetic >> Src Logical ^ Src & Src | Src 15 -213, F’ 02

Some Arithmetic Operations Format Computation One Operand Instructions incl Dest decl Dest negl Dest

Some Arithmetic Operations Format Computation One Operand Instructions incl Dest decl Dest negl Dest notl Dest – 34 – Dest = = Dest + 1 Dest - 1 - Dest ~ Dest 15 -213, F’ 02

Using leal for Arithmetic Expressions int arith (int x, int y, int z) {

Using leal for Arithmetic Expressions int arith (int x, int y, int z) { int t 1 = x+y; int t 2 = z+t 1; int t 3 = x+4; int t 4 = y * 48; int t 5 = t 3 + t 4; int rval = t 2 * t 5; return rval; } – 35 – arith: pushl %ebp movl %esp, %ebp movl 8(%ebp), %eax movl 12(%ebp), %edx leal (%edx, %eax), %ecx leal (%edx, 2), %edx sall $4, %edx addl 16(%ebp), %ecx leal 4(%edx, %eax), %eax imull %ecx, %eax movl %ebp, %esp popl %ebp ret Set Up Body Finish 15 -213, F’ 02

Understanding arith int arith (int x, int y, int z) { int t 1

Understanding arith int arith (int x, int y, int z) { int t 1 = x+y; int t 2 = z+t 1; int t 3 = x+4; int t 4 = y * 48; int t 5 = t 3 + t 4; int rval = t 2 * t 5; return rval; } – 36 – movl 8(%ebp), %eax movl 12(%ebp), %edx leal (%edx, %eax), %ecx leal (%edx, 2), %edx sall $4, %edx addl 16(%ebp), %ecx leal 4(%edx, %eax), %eax imull %ecx, %eax # # # # Offset • • • 16 z 12 y 8 x 4 Rtn adr 0 Old %ebp eax edx ecx eax = = = = x y x+y (t 1) 3*y 48*y (t 4) z+t 1 (t 2) 4+t 4+x (t 5) t 5*t 2 (rval) Stack %ebp 15 -213, F’ 02

Understanding arith int arith (int x, int y, int z) { int t 1

Understanding arith int arith (int x, int y, int z) { int t 1 = x+y; int t 2 = z+t 1; int t 3 = x+4; int t 4 = y * 48; int t 5 = t 3 + t 4; int rval = t 2 * t 5; return rval; } – 37 – # eax = x movl 8(%ebp), %eax # edx = y movl 12(%ebp), %edx # ecx = x+y (t 1) leal (%edx, %eax), %ecx # edx = 3*y leal (%edx, 2), %edx # edx = 48*y (t 4) sall $4, %edx # ecx = z+t 1 (t 2) addl 16(%ebp), %ecx # eax = 4+t 4+x (t 5) leal 4(%edx, %eax), %eax # eax = t 5*t 2 (rval) imull %ecx, %eax 15 -213, F’ 02

Another Example int logical(int x, int y) { int t 1 = x^y; int

Another Example int logical(int x, int y) { int t 1 = x^y; int t 2 = t 1 >> 17; int mask = (1<<13) - 7; int rval = t 2 & mask; return rval; } logical: pushl %ebp movl %esp, %ebp movl xorl sarl andl movl %ebp, %esp popl %ebp ret 213 = 8192, 213 – 7 = 8185 movl xorl sarl andl – 38 – 8(%ebp), %eax 12(%ebp), %eax $17, %eax $8185, %eax eax eax = = Set Up Body Finish x x^y (t 1) t 1>>17 (t 2) t 2 & 8185 15 -213, F’ 02

CISC Properties Instruction can reference different operand types n Immediate, register, memory Arithmetic operations

CISC Properties Instruction can reference different operand types n Immediate, register, memory Arithmetic operations can read/write memory Memory reference can involve complex computation n n Rb + S*Ri + D Useful for arithmetic expressions, too Instructions can have varying lengths n – 39 – IA 32 instructions can range from 1 to 15 bytes 15 -213, F’ 02

Summary: Abstract Machines Machine Models C mem proc Assembly mem Stack – 40 –

Summary: Abstract Machines Machine Models C mem proc Assembly mem Stack – 40 – regs alu Cond. processor Codes Data 1) char 2) int, float 3) double 4) struct, array 5) pointer Control 1) loops 2) conditionals 3) switch 4) Proc. call 5) Proc. return 1) byte 3) branch/jump 2) 2 -byte word 4) call 3) 4 -byte long word 5) ret 4) contiguous byte allocation 5) address of initial byte 15 -213, F’ 02

Pentium Pro (P 6) History n Announced in Feb. ‘ 95 n Basis for

Pentium Pro (P 6) History n Announced in Feb. ‘ 95 n Basis for Pentium II, Pentium III, and Celeron processors Pentium 4 similar idea, but different details n Features n Dynamically translates instructions to more regular format l Very wide, but simple instructions n Executes operations in parallel l Up to 5 at once n Very deep pipeline l 12– 18 cycle latency – 41 – 15 -213, F’ 02

Pentium. Pro Block Diagram Microprocessor Report 2/16/95

Pentium. Pro Block Diagram Microprocessor Report 2/16/95

Pentium. Pro Operation Translates instructions dynamically into “Uops” n 118 bits wide n Holds

Pentium. Pro Operation Translates instructions dynamically into “Uops” n 118 bits wide n Holds operation, two sources, and destination Executes Uops with “Out of Order” engine n Uop executed when l Operands available l Functional unit available n Execution controlled by “Reservation Stations” l Keeps track of data dependencies between uops l Allocates resources Consequences n n – 43 – Indirect relationship between IA 32 code & what actually gets executed Tricky to predict / optimize performance at assembly level 15 -213, F’ 02

Whose Assembler? Intel/Microsoft Format GAS/Gnu Format lea sub cmp mov leal subl cmpl movl

Whose Assembler? Intel/Microsoft Format GAS/Gnu Format lea sub cmp mov leal subl cmpl movl eax, [ecx+ecx*2] esp, 8 dword ptr [ebp-8], 0 eax, dword ptr [eax*4+100 h] (%ecx, 2), %eax $8, %esp $0, -8(%ebp) $0 x 100(, %eax, 4), %eax Intel/Microsoft Differs from GAS n Operands listed in opposite order mov Dest, Src n Constants not preceded by ‘$’, Denote hex with ‘h’ at end 100 h n $0 x 100 Operand size indicated by operands rather than operator suffix sub n subl Addressing format shows effective address computation [eax*4+100 h] – 44 – movl Src, Dest $0 x 100(, %eax, 4) 15 -213, F’ 02